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dBCool Remote Thermal Monitor and Fan Controller ADT7467
FEATURES
Controls and monitors up to 4 fans High and low frequency fan drive signal 1 on-chip and 2 remote temperature sensors Series resistance cancellation on the remote channel Extended temperature measurement range, up to 191C Dynamic TMIN control mode intelligently optimizes system acoustics Automatic fan speed control mode manages system cooling based on measured temperature Enhanced acoustic mode dramatically reduces user perception of changing fan speeds Thermal protection feature via THERM output Monitors performance impact of Intel Pentium 4 processor Thermal control circuit via THERM input 2-wire, 3-wire, and 4-wire fan speed measurement Limit comparison of all monitored values Meets SMBus 2.0 electrical specifications (fully SMBus 1.1 compliant)
GENERAL DESCRIPTION
The ADT7467 dBCool(R) controller is a thermal monitor and multiple PWM fan controller for noise-sensitive or powersensitive applications requiring active system cooling. The ADT7467 can drive a fan using either a low or high frequency drive signal, monitor the temperature of up to two remote sensor diodes plus its own internal temperature, and measure and control the speed of up to four fans so that they operate at the lowest possible speed for minimum acoustic noise. The automatic fan speed control loop optimizes fan speed for a given temperature. A unique dynamic TMIN control mode enables the system thermals/acoustics to be intelligently managed. The effectiveness of the system's thermal solution can be monitored using the THERM input. The ADT7467 also provides critical thermal protection to the system using the bidirectional THERM pin as an output to prevent system or component overheating.
FUNCTIONAL BLOCK DIAGRAM
SCL SDA SMBALERT
SERIAL BUS INTERFACE AUTOMATIC FAN SPEED CONTROL ADDRESS POINTER REGISTER
PWM1 PWM2 PWM3 TACH1 TACH2 TACH3 TACH4
PWM REGISTERS AND CONTROLLERS HF & LF
ACOUSTIC ENHANCEMENT CONTROL
DYNAMIC TMIN CONTROL FAN SPEED COUNTER
PWM CONFIGURATION REGISTERS
INTERRUPT MASKING PERFORMANCE MONITORING
THERM VCC D1+ D1- D2+ D2- VCCP BAND GAP TEMP SENSOR SRC VCC TO ADT7467
THERMAL PROTECTION
ADT7467
INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER 10-BIT ADC
INTERRUPT STATUS REGISTERS
LIMIT COMPARATORS
BAND GAP REFERENCE GND
VALUE AND LIMIT REGISTERS
04498-001
Figure 1.
(c)2008 SCILLC. All rights reserved. January 2008 - Rev. 3
Publication Order Number: ADT7467/D
ADT7467 TABLE OF CONTENTS
Features...............................................................................................1 General Description..........................................................................1 Functional Block Diagram...............................................................1 Revision History................................................................................2 Specifications .....................................................................................3 Absolute Maximum Ratings ............................................................5 Thermal Characteristics...............................................................5 ESD Caution ..................................................................................5 Pin Configuration and Function Descriptions .............................6 Typical Performance Characteristics..............................................7 Product Description .........................................................................9 Comparison Between ADT7460 and ADT7467.......................9 Recommended Implementation ...............................................10 Serial Bus Interface .........................................................................11 Write Operations.........................................................................13 Read Operations..........................................................................13 SMBus Timeout...........................................................................14 Analog-to-Digital Converter .........................................................15 Voltage Measurement Input ......................................................15 Additional ADC Functions for Voltage Measurements.........15 Temperature Measurement........................................................16 Series Resistance Cancellation ..................................................17 Additional ADC Functions for Temperature Measurement.19 Limits, Status Registers, and Interrupts .......................................21 Limit Values .................................................................................21 Status Registers............................................................................22 Interrupts .....................................................................................22 Active Cooling .................................................................................27 Driving the Fan Using PWM Control......................................27 Laying Out 2-Wire and 3-Wire Fans........................................29 Fan Speed Measurement ............................................................30 Fan Spin-Up.................................................................................31 PWM Logic State ........................................................................32 Fan Speed Control ......................................................................33 Miscellaneous Functions................................................................34 Operating from 3.3 V Standby..................................................34 XNOR Tree Test Mode ...............................................................34 Power-On Default .......................................................................34 Automatic Fan Control Overview ................................................35 Dynamic TMIN Control Mode ....................................................36 Programming the Automatic Fan Speed Control Loop.............38 Step 1: Hardware Configuration ...............................................38 Step 2: Configuring the Mux.....................................................40 Step 3: TMIN Settings for Thermal Calibration Channels .......42 Step 4: PWMMIN for PWM (Fan) Outputs ...............................43 Step 5: PWMMAX for PWM (Fan) Outputs ..............................44 Step 6: TRANGE for Temperature Channels ................................45 Step 7: TTHERM for Temperature Channels................................47 Step 8: THYST for Temperature Channels ..................................49 Step 9: Operating Points for Temperature Channels .............50 Step 10: High and Low Limits for Temperature Channels....51 Step 11: Monitoring THERM....................................................53 Step 12: Ramp Rate for Acoustic Enhancement .....................54 Enhancing System Acoustics .........................................................57 Acoustic Enhancement Mode Overview.................................57 Register Map ....................................................................................59 ADT7467 Programming Block Diagram.....................................76 Outline Dimensions........................................................................77 Ordering Guide ...........................................................................77
REVISION HISTORY
01/08 - Rev 3: Conversion to ON Semiconductor 12/07--Rev. A to Rev. B Changes to Limit Values Section Changes to Table 13 Changes to Figure 34 and Figure 36 Changes to Figure 41 Changes to Step 11: Monitoring THERM Section Changes to Table 26 Changes to Table 30 Changes to Table 37 Changes to Table 38 Changes to Table 41 and Table 42 Changes to Table 52 and Table 53 Changes to Table 54 Changes to Figure 84 Updated Outline Dimensions Changes to Ordering Guide 7/05--Rev. 0 to Rev. A Change to Absolute Maximum Ratings Change to Recommended Implementation Section Changes to Recommended Implementation Figure Deleted Recommended Implementation 2 Section Deleted Recommended Implementation 2 Figure Change to Table 17 Changes to Ordering Guide 4/04--Revision 0: Initial Version
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ADT7467 SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25C and represent the most likely parametric norm. Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by design and are not production tested. Table 1.
Parameter POWER SUPPLY Supply Voltage Supply Current, ICC TEMPERATURE-TO-DIGITAL CONVERTER Local Sensor Accuracy -3.5 -4 Resolution Remote Diode Sensor Accuracy -3.5 -4.5 Resolution Remote Sensor Source Current 0.25 6 36 96 0.25 0.5 Min 3.0 Typ 3.3 Max 5.5 3 20 1.5 +2 +2 1.5 +2 +2 Unit V mA A C C C C C C C C A Test Conditions/Comments
Interface inactive, ADC active Standby mode 0C TA 70C -40C TA +100C -40C TA +120C 0C TA 70C; 0C TD 120C 0C TA 105C; 0C TD 120C -40C TA +120C; 0C TD +120C First current Second current Third current
ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS) Total Unadjusted Error (TUE) Differential Nonlinearity (DNL) Power Supply Sensitivity Conversion Time (Voltage Input) Conversion Time (Local Temperature) Conversion Time (Remote Temperature) Total Monitoring Cycle Time Input Resistance FAN RPM-TO-DIGITAL CONVERTER Accuracy 40 80
1.5 1 0.1 11 12 38 145 19 80 140
100 200 5 7 10 65,535
% LSB %/V ms ms ms ms ms k k % % % RPM RPM RPM RPM
8 bits Averaging enabled Averaging enabled Averaging enabled Averaging enabled Averaging disabled For VCC channel For all channels other than VCC 0C TA 70C, 3.3 V -40C TA +120C, 3.3 V -40C TA +120C, 5.5 V Fan count = 0xBFFF Fan count = 0x3FFF Fan count = 0x0438 Fan count = 0x021C 0C TA 70C, VCC = 3.3 V -40C TA +120C, VCC = 3.3 V -40C TA +120C, VCC = 5.5 V
Full-Scale Count Nominal Input RPM
109 329 5000 10,000 85.5 83.7 81 90 90 90 94.5 96.3 99
Internal Clock Frequency
kHz kHz kHz
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ADT7467
Parameter OPEN-DRAIN DIGITAL OUTPUTS, PWM1 to PWM3, XTO Current Sink, IOL Output Low Voltage, VOL High Level Output Current, IOH OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Current, IOH SMBus DIGITAL INPUTS (SCL, SDA) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (TACH INPUTS) Input High Voltage, VIH Input Low Voltage, VIL -0.3 Hysteresis DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+ Input High Voltage, VIH Input Low Voltage, VIL DIGITAL INPUT CURRENT Input High Current, IIH Input Low Current, IIL Input Capacitance, CIN SERIAL BUS TIMING Clock Frequency, fSCLK Glitch Immunity, tSW Bus Free Time, tBUF Start Setup Time, tSU; STA Start Hold Time, tHD; STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tf Data Setup Time, tSU; DAT Data Hold Time, tHD; DAT Detect Clock Low Timeout, tTIMEOUT
tR
Min
Typ
Max
Unit
Test Conditions/Comments
0.1
8.0 0.4 1.0 0.4 1.0
mA V A V A V V mV V V V V V p-p V V A A pF kHz ns s s s s s ns s ns ns ms
IOUT = -8.0 mA, VCC = 3.3 V VOUT = VCC IOUT = -4.0 mA, VCC = 3.3 V VOUT = VCC
0.1 2.0
0.4 500 2.0 5.5 0.8 0.5 0.75 x VCCP 0.4 -1 1 5 10 4.7 4.7 4.0 4.7 4.0 400 50
Maximum input voltage Minimum input voltage
VIN = VCC VIN = 0 See Figure 2
50 1000 300
250 300 15
tF
35
Can be optionally disabled
tLOW
SCL
tHD; STA
tHD; STA
tHD; DAT
tHIGH
tSU; DAT
tSU; STA
tSU; STO
P
S
S
P
Figure 2. Serial Bus Timing Diagram
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04498-002
SDA
tBUF
ADT7467 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Positive Supply Voltage (VCC) Voltage on Any Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJMAX) Storage Temperature Range Lead Temperature, Soldering IR Reflow Peak Temperature For Pb-free models Lead Temperature (Soldering, 10 sec) ESD Rating Rating 5.5 V -0.3 V to +6.5 V 5 mA 20 mA 150C -65C to +150C 220C 260C 300C 1000 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
16-lead QSOP package: JA = 150C/W JC = 39C/W
ESD CAUTION
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ADT7467 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SCL 1 GND 2 VCC 3 TACH3 4 PWM2/SMBALERT 5 TACH1 6 TACH2 7 PWM3 8
16 15 14
SDA PWM1/XTO VCCP D1+ D1- D2+ D2- TACH4/GPIO/THERM/SMBALERT
04498-003
ADT7467
(Not to Scale)
TOP VIEW
13 12 11 10 9
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 Mnemonic SCL GND VCC Description Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. Ground Pin for the ADT7467. Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. VCC is also monitored through this pin. The ADT7467 can also be powered from a 5 V supply. Setting Bit 7 of Configuration Register 1 (0x40) rescales the VCC input attenuators to correctly measure a 5 V supply. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. Can be reconfigured as an analog input (AIN3) to measure the speed of 2-wire fans (low frequency mode only). Digital Output (Open Drain). Requires 10 k typical pull-up. Pulse width modulated output to control the speed of Fan 2. Can be configured as a high or low frequency drive. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. Can be reconfigured as an analog input (AIN1) to measure the speed of 2-wire fans (low frequency mode only). Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. Can be reconfigured as an analog input (AIN2) to measure the speed of 2-wire fans (low frequency mode only). Digital I/O (Open Drain). Pulse width modulated output to control the speed of Fan 3 and Fan 4. Requires 10 k typical pull-up. Can be configured as a high or low frequency drive. Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Can be reconfigured as an analog input (AIN4) to measure the speed of 2-wire fans (low frequency mode only). General-Purpose Open-Drain Digital I/O. Alternatively, the pin can be reconfigured as a bidirectional THERM pin, which can be used to time and monitor assertions on the THERM input. For example, the pin can be connected to the PROCHOT output of an Intel(R) Pentium(R) 4 processor or to the output of a trip point temperature sensor. This pin can be used as an output to signal overtemperature conditions. Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-limit conditions. Cathode Connection to Second Thermal Diode. Anode Connection to Second Thermal Diode. Cathode Connection to First Thermal Diode. Anode Connection to First Thermal Diode. Analog Input. Monitors processor core voltage (0 V to 3 V). Digital Output (Open Drain). Pulse width modulated output to control the speed of Fan 1. Requires 10 k typical pull-up. Also functions as the output from the XNOR tree in XNOR test mode. Digital I/O (Open Drain). SMBus bidirectional serial data. Requires 10 k typical pull-up.
4 5
TACH3 PWM2 SMBALERT
6 7 8 9
TACH1 TACH2 PWM3 TACH4 GPIO THERM
SMBALERT 10 11 12 13 14 15 D2- D2+ D1- D1+ VCCP PWM1 XTO SDA
16
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ADT7467 TYPICAL PERFORMANCE CHARACTERISTICS
0 20
100mV
-10
15 TEMPERATURE ERROR (C)
TEMPERATURE ERROR (C)
-20
10
40mV
-30
5
-40
0
-50
-5
60mV
04498-045
0
1
2.2 3.3 CAPACITANCE (nF)
4.7
10
100k
1M 10M FREQUENCY (kHz)
100M
1G
Figure 4. Temperature Error vs. Capacitance Between D+ and D-
Figure 7. Remote Temperature Error vs. Common-Mode Noise Frequency
0 -10 -20
6 5 4 TEMPERATURE ERROR (C) 3 2 1 0 -1 -2 -3
04498-046
20mV
TEMPERATURE ERROR (C)
-30 -40 -50 -60 -70 -80 -90
10mV
0
5
10 15 CAPACITANCE (nF)
20
25
100k
1M 10M FREQUENCY (kHz)
100M
1G
Figure 5. External Temperature Error vs. Capacitance Between D+ and D-
Figure 8. Remote Temperature Error vs. Differential Mode Noise Frequency
60 40 TEMPERATURE ERROR (C) 20 0 -20 -40 -60 -80
D+ TO GND
1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 POWER SUPPLY VOLTAGE (V)
D+ TO VCC
Figure 6. Temperature Error vs. PCB Resistance
Figure 9. Normal IDD vs. Power Supply
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04498-050
0
1
3.3
10 RESISTANCE (M)
20
100
04498-047
IDD (mA)
04498-049
-100
-4 10k
04498-048
-60
-10 10k
ADT7467
7 6 5 4 3 2 1 0 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 POWER SUPPLY VOLTAGE (V)
1.0 0.5 0
TEMPERATURE ERROR (C)
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -20 0 20 40 60 TEMPERATURE (C) 80 100 120
04498-091 04498-092
IDD (A)
Figure 10. Shutdown IDD vs. Power Supply
04498-051
-4.0 -40
Figure 13. Internal Temperature Error vs. Temperature
20 15 TEMPERATURE ERROR (C)
1.0 0.5 0
INT ERROR, 250mV
TEMPERATURE ERROR (C)
1G
04498-052
10 5 0 -5 -10 -15 -20 10k
INT ERROR, 100mV
-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5
100k 1M 10M 100M POWER SUPPLY NOISE FREQUENCY (kHz)
-4.0 -40
-20
0
20 40 60 TEMPERATURE (C)
80
100
120
Figure 11. Internal Temperature Error vs. Power Supply Noise Frequency
Figure 14. Remote Temperature Error vs. Temperature
20
EXT ERROR, 250mV
15 TEMPERATURE ERROR (C) 10 5 0 -5 -10 -15 -20 10k
EXT ERROR, 100mV
100k 1M 10M 100M POWER SUPPLY NOISE FREQUENCY (kHz)
1G
Figure 12. Remote Temperature Error vs. Power Supply Noise Frequency
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04498-053
ADT7467 PRODUCT DESCRIPTION
The ADT7467 is a complete thermal monitor and multiple fan controller for systems requiring thermal monitoring and cooling. The device communicates with the system via a serial system management bus. The serial bus controller has a serial data line for reading and writing addresses and data (Pin 16) and an input line for the serial clock (Pin 1). All control and programming functions for the ADT7467 are performed over the serial bus. In addition, one of two pins can be reconfigured as an SMBALERT output to signal out-of-limit conditions. The ADT7467 has an extended temperature measurement range. The measurement range goes from -64C to +191C. On the ADT7460, the measurement range is from -127C to +127C. This means that the ADT7467 can measure higher temperatures. The ADT7467 also includes the ADT7460 temperature range; the temperature measurement range can be switched by setting Bit 0 of Configuration Register 5. 6. The ADT7467 maximum fan speed (% duty cycle) in the automatic fan speed control loop can be programmed. The maximum fan speed is 100% duty cycle on the ADT7460 and is not programmable. 7. The offset register in the ADT7467 is programmable up to 64C with 0.50C resolution. The offset register of the ADT7460 is programmable up to 32C with 0.25C resolution. 8. VCCP is monitored on Pin 14 of the ADT7467 and can be used to set the threshold for THERM (PROCHOT) (2/3 of VCCP). 2.5 V is monitored on Pin 14 of the ADT7460. The threshold for THERM (PROCHOT) is set at VIH = 1.7 V and VIL = 0.8 V on the ADT7460. 9. On the ADT7460, Pin 14 could be reconfigured as SMBALERT. This is not available on the ADT7467. SMBALERT can be enabled instead on Pin 9. 10. A GPIO can also be made available on Pin 9 on the ADT7467. This is not available on the ADT7460. Set the GPIO polarity and direction in Configuration Register 5. The GPIO status bit is Bit 5 of Status Register 2 (it is shared with TACH4 and THERM because only one can be enabled at a time). 11. The ADT7460 has three possible SMBus addresses, which are selectable using the address select and address enable pins. The ADT7467 has one SMBus address available at Address 0x2E. Due to the inclusion of extra functionality, the register map has changed, including an additional configuration register, Configuration Register 5 at Address 0x7C. 5.
COMPARISON BETWEEN ADT7460 AND ADT7467
The ADT7467 is an upgrade from the ADT7460. The ADT7467 and ADT7460 are almost pin and register map compatible. The ADT7467 and ADT7460 have the following differences: 1. On the ADT7467, the PWM drive signals can be configured as either high frequency or low frequency drives. The low frequency option is programmable between 10 Hz and 100 Hz. The high frequency option is 22.5 kHz. On the ADT7460, only the low frequency option is available. Once VCC and VCCP are powered up, monitoring of temperature and fan speeds is enabled on the ADT7467. If VCCP is never powered up, monitoring is enabled when the first SMBus transaction with the ADT7467 is complete. On the ADT7460, the STRT bit in Configuration Register 1 must be set to enable monitoring. The fans are switched off by default upon power-up of the ADT7467. On the ADT7460, the fans run at full speed upon power-up. Fail-safe cooling is provided on the ADT7467. If the measured temperature exceeds the THERM limit (100C), the fans run at full speed. Fail-safe cooling is also provided 4.6 sec after VCCP is powered up. The fans operate at full speed if the ADT7467 has not been addressed via the SMBus within 4.6 sec of when the VCCP is powered up. This protects the system in the event that the SMBus fails. The ADT7467 can be programmed at any time, and it behaves as programmed. If VCCP is never powered up, fail-safe cooling is effectively disabled. If VCCP is disabled, writing to the ADT7467 at any time causes the ADT7467 to operate normally. 4. Series resistance cancellation (SRC) is provided on the remote temperature channels on the ADT7467, but not on the ADT7460. SRC automatically cancels linear offset introduced by a series resistance between the thermal diode and the sensor.
2.
3.
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ADT7467
Configuration Register 5
Bit 0: If Bit 0 is set to 1, the ADT7467, in terms of temperature, is backward compatible with the ADT7460. Measurements, including TMIN calibration circuit and fan control, work in the range -127C to +127C. In addition, care should be taken in reprogramming the temperature limits (TMIN, operating point, THERM) to their desired twos complement value, because the power-on default for them is at Offset 64. The extended temperature range is -64C to 191C. The default is 1, which is in the -64C to +191C temperature range. Bit 1 = 0 is the high frequency (22.5 kHz) fan drive signal. Bit 1 = 1 switches the fan drive to low frequency PWM, programmable between 10 Hz and 100 Hz, the same as the ADT7460. The default is 0, or HF PWM. Bit 2 sets the direction for the GPIO: 0 = input, 1 = output. Bit 3 sets the GPIO polarity: 0 = active low, 1 = active high. Table 4. Pin 9 Settings
Bit 1 0 0 1 1 Bit 0 0 1 0 1 Function TACH4 THERM SMBALERT GPIO
RECOMMENDED IMPLEMENTATION
Configuring the ADT7467 as in Figure 15 allows the system designer to use the following features: * * * * * * Two PWM outputs for fan control of up to three fans (the front and rear chassis fans are connected in parallel). Three TACH fan speed measurement inputs. VCC measured internally through Pin 3. CPU temperature measured using the Remote 1 temperature channel. Ambient temperature measured through the Remote 2 temperature channel. Bidirectional THERM pin. This feature allows Intel Pentium 4 PROCHOT monitoring and can function as an overtemperature THERM output. Alternatively, it can be programmed as an SMBALERT system interrupt output.
Setting the Functionality of Pin 9
Pin 9 on the ADT7467 has four possible functions: SMBALERT, THERM, GPIO, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D.
FRONT CHASSIS FAN
ADT7467
TACH2 PWM1 TACH1
CPU FAN
REAR CHASSIS FAN
PWM3 TACH3 D2+ D2- THERM D1+ D1- PROCHOT
AMBIENT TEMPERATURE
CPU
SDA SCL SMBALERT
04498-004
GND
ICH
Figure 15. ADT7467 Configuration
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ADT7467 SERIAL BUS INTERFACE
On PCs and servers, control of the ADT7467 is carried out using the serial system management bus (SMBus). The ADT7467 is connected to this bus as a slave device under the control of a master controller, which is usually (but not necessarily) the ICH. The ADT7467 has a fixed 7-bit serial bus address of 0101110 or 0x2E. The read/write bit must be added to get the 8-bit address (01011100 or 0x5C). Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition might be interpreted as a stop signal when the clock is high. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is only limited by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the ninth clock pulse. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse, and then high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation. It is not possible to mix a read and a write in one operation, however, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. In the ADT7467, write operations contain either one or two bytes, and read operations contain one byte. To write data to a device data register or read data from it, the address pointer register must first be set. The first byte of a write operation always contains an address, which is stored in the address pointer register, and the second byte, if there is a second byte, is written to the register selected by the address pointer register. This write operation is illustrated in Figure 16. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register, and the second data byte is the data written to that internal data register. When reading data from a register, there are two possibilities: * If the address pointer register value of the ADT7467 is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is achieved by writing a data byte containing the register address to the ADT7467. This is shown in Figure 17. A read operation is then performed consisting of the serial bus address and the R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 18. If the address pointer register is known to be at the desired address, data can be read from the corresponding data register without first writing to the address pointer register, as shown in Figure 18.
*
If the address pointer register is already at the correct value, it is possible to read a data byte from the data register without first writing to the address pointer register. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7467 also supports the read byte protocol. (See the Intel System Management Bus Specifications Rev. 2 for more information.) If several read or write operations must be performed in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.
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ADT7467
1 SCL 9 1 9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7467
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7467
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
1 SCL (CONTINUED)
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
04498-005
04498-007 04498-006
FRAME 3 DATA BYTE
ACK. BY ADT7467
STOP BY MASTER
Figure 16. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCL
9
1
9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7467
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7467 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 17. Writing to the Address Pointer Register Only
1 SCL
9
1
9
SDA START BY MASTER
0
1
0
1
1
1
0
R/W ACK. BY ADT7467
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. BY STOP BY MASTER MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADT7467
Figure 18. Reading Data from a Previously Selected Register
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ADT7467
WRITE OPERATIONS
The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7467 are discussed here. The following abbreviations are used in Figure 19 through Figure 21: S = start P = stop R = read W = write A = acknowledge A = no acknowledge The ADT7467 uses the following SMBus write protocols. 3. 4. 5. 6. 7. 8. The addressed slave device asserts an acknowledge on SDA. The master sends a command code. The slave asserts an acknowledge on SDA. The master sends a data byte. The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 SLAVE ADDRESS 5 6 78
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This operation is illustrated in Figure 20.
SLAVE S WA ADDRESS A DATA A P
Figure 20. Single Byte Write to a Register
Send Byte
In this operation, the master device sends a single command byte to a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an acknowledge on SDA. The master sends a command code. The slave asserts an acknowledge on SDA. The master asserts a stop condition on SDA, and the transaction ends.
READ OPERATIONS
The ADT7467 uses the following SMBus read protocols.
Receive Byte
This operation is useful when repeatedly reading a single register. The register address must have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts an acknowledge on SDA. The master receives a data byte. The master asserts a no acknowledge on SDA. The master asserts a stop condition on SDA, and the transaction ends.
For the ADT7467, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This operation is illustrated in Figure 19.
1 2 3 4 REGISTER ADDRESS 56 AP
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SLAVE S WA ADDRESS
Figure 19. Setting a Register Address for Subsequent Read
If the master is required to read data from the register directly after setting up the address, it can assert a repeat start condition immediately after the final acknowledge and carry out a single byte read without asserting an intermediate stop condition.
In the ADT7467, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. This operation is illustrated in Figure 21.
1 2 3 4 5 6
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SLAVE S R A DATA A P ADDRESS
Figure 21. Single Byte Read from a Register
Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. 2. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low).
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ADT7467
Alert Response Address
Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device's SMBALERT line goes low, the following procedure occurs: 1. 2. SMBALERT is pulled low. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. 4. If more than one device's SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. Once the ADT7467 has responded to the alert response address, the master must read the status registers. The SMBALERT is cleared only if the error condition is absent.
5.
SMBus TIMEOUT
The ADT7467 includes an SMBus timeout feature. If there is no SMBus activity for 35 ms, the ADT7467 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus in anticipation of receiving data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled.
3.
Configuration Register 1 (0x40)
<6> TODIS = 0, SMBus timeout enabled (default) <6> TODIS = 1, SMBus timeout disabled
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ADT7467 ANALOG-TO-DIGITAL CONVERTER
All analog inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter, which has a resolution of 10 bits. The basic input range is 0 V to 2.25 V, but the input has built-in attenuators to allow measurement of VCCP without any external components. To allow for the tolerance of the supply voltage, the ADC produces an output of 3/4 full scale (decimal 768 or 300 hexadecimal) for the nominal input voltage and, therefore, has adequate headroom to deal with overvoltages. When the ADC is running, it samples and converts a voltage input in 0.7 ms and averages 16 conversions to reduce noise; a measurement takes nominally 11 ms.
ADDITIONAL ADC FUNCTIONS FOR VOLTAGE MEASUREMENTS
A number of other functions are available on the ADT7467 to offer the system designer increased flexibility.
Turn-Off Averaging
For each voltage measurement read from a value register, 16 readings are made internally, the results of which are averaged and then placed into the value register. For instances where faster conversions are needed, setting Bit 4 of Configuration Register 2 (0x73) turns averaging off. This produces a reading that is 16 times faster (0.7 ms), but the reading may be noisier.
VOLTAGE MEASUREMENT INPUT
The ADT7467 has one external voltage measurement channel. It can also measure its own supply voltage, VCC. Pin 14 can measure VCCP. The VCC supply voltage measurement is carried out through the VCC pin (Pin 3). Setting Bit 7 of Configuration Register 1 (0x40) allows a 5 V supply to power the ADT7467 and be measured without overranging the VCC measurement channel. The VCCP input can be used to monitor a chipset supply voltage in computer systems.
Bypass Voltage Input Attenuator
Setting Bit 5 of Configuration Register 2 (0x73) removes the attenuation circuitry from the VCCP input. This allows the user to directly connect external sensors or to rescale the analog voltage measurement inputs for other applications. The input range of the ADC without the attenuators is 0 V to 2.25 V.
Input Circuitry
The internal structure for the VCCP analog input is shown in Figure 22. The input circuit consists of an input protection diode, an attenuator, and a capacitor to form a first-order lowpass filter that gives the input immunity to high frequency noise.
VCCP 17.5k
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Single-Channel ADC Conversion
Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7467 into single-channel ADC conversion mode. In this mode, the ADT7467 can be made to read a single voltage channel only. If the internal ADT7467 clock is used, the selected input is read every 0.7 ms. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55). Table 5. Programming Single-Channel ADC Mode
Bits <7:5>, Register 0x55 001 010 101 110 111 Channel Selected VCCP VCC Remote 1 temperature Local temperature Remote 2 temperature
52.5k
35pF
Figure 22. Structure of Analog Inputs
Voltage Measurement Registers
Register 0x21 VCCP reading = 0x00 default Register 0x22 VCC reading = 0x00 default
VCCP Limit Registers
Associated with the VCCP and VCC measurement channels is a high and low limit register. Exceeding the programmed high or low limit causes the appropriate status bit to be set. Exceeding either limit can also generate SMBALERT interrupts. Register 0x46 VCCP low limit = 0x00 default Register 0x47 VCCP high limit = 0xFF default Register 0x48 VCC low limit = 0x00 default Register 0x49 VCC high limit = 0xFF default
Table 6 shows the input ranges of the analog inputs and output
Configuration Register 2 (0x73)
<4> = 1, averaging off <5> = 1, bypass input attenuators <6> = 1, single-channel conversion mode
TACH1 Minimum High Byte (0x55)
<7:5> selects ADC channel for single-channel convert mode.
codes of the 10-bit ADC.
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ADT7467
Table 6. 10-Bit Analog-to-Digital Output Code vs. VIN
Input Voltage VCC (5 VIN) <0.0065 0.0065 to 0.0130 0.0130 to 0.0195 0.0195 to 0.0260 0.0260 to 0.0325 0.0325 to 0.0390 0.0390 to 0.0455 0.0455 to 0.0521 0.0521 to 0.0586 1.6675 to 1.6740 3.330 to 3.3415 5.0025 to 5.0090 6.5983 to 6.6048 6.6048 to 6.6113 6.6113 to 6.6178 6.6178 to 6.6244 6.6244 to 6.6309 6.6309 to 6.6374 6.6374 to 6.4390 6.6439 to 6.6504 6.6504 to 6.6569 6.6569 to 6.6634 >6.6634 VCC (3.3 VIN) <0.0042 0.0042 to 0.0085 0.0085 to 0.0128 0.0128 to 0.0171 0.0171 to 0.0214 0.0214 to 0.0257 0.0257 to 0.0300 0.0300 to 0.0343 0.0343 to 0.0386 1.100 to 1.1042 2.200 to 2.2042 3.300 to 3.3042 4.3527 to 4.3570 4.3570 to 4.3613 4.3613 to 4.3656 4.3656 to 4.3699 4.3699 to 4.3742 4.3742 to 4.3785 4.3785 to 4.3828 4.3828 to 4.3871 4.3871 to 4.3914 4.3914 to 4.3957 >4.3957 VCCP <0.00293 0.0293 to 0.0058 0.0058 to 0.0087 0.0087 to 0.0117 0.0117 to 0.0146 0.0146 to 0.0175 0.0175 to 0.0205 0.0205 to 0.0234 0.0234 to 0.0263 0.7500 to 0.7529 1.5000 to 1.5029 2.2500 to 2.2529 2.9677 to 2.9707 2.9707 to 2.9736 2.9736 to 2.9765 2.9765 to 2.9794 2.9794 to 2.9824 2.9824 to 2.9853 2.9853 to 2.9882 2.9882 to 2.9912 2.9912 to 2.9941 2.9941 to 2.9970 >2.9970 Decimal 0 1 2 3 4 5 6 7 8 ... 256 (1/4 scale) ... 512 (1/2 scale) ... 768 (3/4 scale) ... 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 A/D Output Binary (10 Bits) 00000000 00 00000000 01 00000000 10 00000000 11 00000001 00 00000001 01 00000001 10 00000001 11 00000010 00 01000000 00 10000000 00 11000000 00 11111101 01 11111101 10 11111101 11 11111110 00 11111110 01 11111110 10 11111110 11 11111111 00 11111111 01 11111111 10 11111111 11
TEMPERATURE MEASUREMENT
A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor operated at constant current. Unfortunately, this technique requires calibration to null the effect of the absolute value of VBE, which varies from each device. The technique used in the ADT7467 is to measure the change in VBE when the device is operated at three currents. Previous devices have used only two operating currents, but the use of a third current allows automatic cancellation of resistances in series with the external temperature sensor. Figure 24 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to
ground but is biased above ground by an internal diode at the D- input. C1 can optionally be added as a noise filter (the recommended maximum value is 1000 pF). However, a better option in noisy environments is to add a filter as described in the Noise Filtering section.
Local Temperature Measurement
The ADT7467 contains an on-chip band gap temperature sensor whose output is digitized by the on-chip 10-bit ADC. The 8-bit MSB temperature data is stored in the local temperature register (Address 0x26). Because both positive and negative temperatures can be measured, the temperature data is stored in Offset 64 format or twos complement format, as shown in Table 7 and Table 8. Theoretically, the temperature sensor and ADC can measure temperatures from -128C to +127C (or -64C to +191C in the extended temperature range) with a resolution of 0.25C. However, this exceeds the operating temperature range of the device, preventing local temperature measurements outside the ADT7467 operating temperature range.
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ADT7467
Remote Temperature Measurement
The ADT7467 can measure the temperature of two remote diode sensors or diode-connected transistors connected to Pin 10 and Pin 11 or to Pin 12 and Pin 13. The forward voltage of a diode or diode-connected transistor operated at a constant current exhibits a negative temperature coefficient of about -2 mV/C. Unfortunately, the absolute value of VBE varies from each device and thus requires individual calibration; therefore, the technique is unsuitable for mass production. The technique used in the ADT7467 is to measure the change in VBE when the device is operated at three currents. This is given by VBE = kT/q x ln(N) where: k is Boltzmann's constant. q is the charge on the carrier. T is the absolute temperature in Kelvin. N is the ratio of the two currents. Figure 23 shows the input signal conditioning used to measure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor provided for temperature monitoring on some microprocessors. It could also be a discrete transistor such as a 2N3904/2N3906.
I REMOTE SENSING TRANSISTOR D+ D- LPF fC = 65kHz VOUT+ TO ADC VOUT-
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I and N2 x I, resulting in VBE2. The temperature can then be calculated using the two VBE measurements. This method can also cancel the effect of series resistance on the temperature measurement. The resulting VBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then sent to a chopperstabilized amplifier that amplifies and rectifies the waveform to produce a dc voltage proportional to VBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. The results of remote temperature measurements are stored in 10-bit twos complement format, as listed in Table 7. The extra resolution for the temperature measurements is held in the Extended Resolution Register 2 (0x77). This produces temperature readings with a resolution of 0.25C.
SERIES RESISTANCE CANCELLATION
Parasitic resistance to the ADT7467 D+ and D- inputs (seen in series with the remote diode) is caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor's temperature measurement. This error typically causes a 0.5C offset per 1 of parasitic resistance in series with the remote diode. The ADT7467 automatically cancels the effect of this series resistance on the temperature reading, providing a more accurate result without the need for user characterization of this resistance. The ADT7467 is designed to automatically cancel, typically up to 3 k of resistance. By using an advanced temperature measurement method, this is transparent to the user. This feature allows resistances to be added to the sensor path to produce a filter, allowing the part to be used in noisy environments. See the Noise Filtering section for details.
N2 x I N1 x I IBIAS
VDD
Figure 23. Signal Conditioning for Remote Diode Temperature Sensors
If a discrete transistor is used, the collector is not grounded and should be linked to the base. If a PNP transistor is used, the base is connected to the D- input and the emitter is connected to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base is connected to the D+ input. Figure 25 and Figure 26 show how to connect the ADT7467 to an NPN or PNP transistor for temperature measurement. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D- input. To measure VBE, the operating current through the sensor is switched among three related currents. Shown in Figure 23, N1 x I and N2 x I are different multiples of the current I. The currents through the temperature diode are switched between I and N1 x I, resulting in VBE1; then they are switched between
Noise Filtering
For temperature sensors operating in noisy environments, previous practice involved placing a capacitor across the D+ and D- pins to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. A capacitor of this value reduces the noise but does not eliminate it, making use of the sensor difficult in a very noisy environment. The ADT7467 has a major advantage over other devices for eliminating the effects of noise on the external sensor. Using the series resistance cancellation feature, a filter can be constructed between the external temperature sensor and the device. The effect of filter resistance seen in series with the remote sensor is automatically canceled from the temperature result.
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ADT7467
The construction of a filter allows the ADT7467 and the remote temperature sensor to operate in noisy environments. Figure 24 shows a low-pass R-C-R filter with the following values: R = 100 , C = 1 nF This filtering reduces both common-mode noise and differential noise.
100 REMOTE TEMPERATURE SENSOR 1nF 100 D- D+
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If a discrete transistor is used with the ADT7467, the best accuracy is obtained by choosing devices according to the following criteria: * * * * Base-emitter voltage is greater than 0.25 V at 6 A with the highest operating temperature. Base-emitter voltage is less than 0.95 V at 100 A with the lowest operating temperature. Base resistance is less than 100 . There is a small variation in hFE (for example, 50 to 150) that indicates tight control of VBE characteristics.
Figure 24. Filter Between Remote Sensor and ADT7467
Factors Affecting Diode Accuracy Remote Sensing Diode
The ADT7467 is designed to work with either substrate transistors built into processors or discrete transistors. Substrate transistors are generally PNP types with the collector connected to the substrate. Discrete types can be either PNP or NPN transistors connected as a diode (base-shorted to the collector). If an NPN transistor is used, the collector and base are connected to D+ and the emitter is connected to D-. If a PNP transistor is used, the collector and base are connected to D- and the emitter is connected to D+. To reduce the error due to variations in both substrate and discrete transistors, a number of factors should be taken into consideration: * The ideality factor, nf, of the transistor is a measure of the deviation of the thermal diode from ideal behavior. The ADT7467 is trimmed for an nf value of 1.008. Use the following equation to calculate the error introduced at a temperature, T (C), when using a transistor whose nf does not equal 1.008. See the processor's data sheet for the nf values. T = (nf - 1.008)/1.008 x (273.15 K + T) * To correct for this error, the user can write the T value to the offset register, and the ADT7467 automatically adds it to or subtracts it from the temperature measurement. Some CPU manufacturers specify the high and low current levels of the substrate transistors. The high current level of the ADT7467, IHIGH, is 96 A, and the low level current, ILOW, is 6 A. If the ADT7467 current levels do not match the current levels specified by the CPU manufacturer, it may be necessary to remove an offset. The CPU's data sheet should provide information relating to nf to compensate for differences. An offset can be programmed to the offset register. It is important to note that if more than one offset must be considered, the algebraic sum of these offsets must be programmed to the offset register.
Transistors such as 2N3904, 2N3906, or equivalents in SOT-23 packages are suitable devices to use. Table 7. Twos Complement Temperature Data Format
Temperature -128C -125C -100C -75C -50C -25C -10C 0C +10.25C +25.5C +50.75C +75C +100C +125C +127C
1
Digital Output (10-Bit)1 1000 0000 00 1000 0011 00 1001 1100 00 1011 0101 00 1100 1110 00 1110 0111 00 1111 0110 00 0000 0000 00 0000 1010 01 0001 1001 10 0011 0010 11 0100 1011 00 0110 0100 00 0111 1101 00 0111 1111 00
Bold numbers denote 2 LSBs of measurement in Extended Resolution Register 2 (0x77) with 0.25C resolution.
Table 8. Offset 64 Temperature Data Format
Temperature -64C -1C 0C +1C +10C +25C +50C +75C +100C +125C +191C
1
Digital Output (10-Bit)1 0000 0000 00 0011 1111 00 0100 0000 00 0100 0001 00 0100 1010 00 0101 1001 00 0111 0010 00 1000 1001 00 1010 0100 00 1011 1101 00 1111 1111 00
*
Bold numbers denote 2 LSBs of measurement in Extended Resolution Register 2 (0x77) with 0.25C resolution.
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ADT7467
ADT7467
2N3904 NPN D+
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D-
Figure 25. Measuring Temperature Using an NPN Transistor
ADT7467
2N3906 PNP D+
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Temperature Measurement Registers Register 0x25 Remote 1 temperature = 0x01 default Register 0x26 local temperature = 0x01 default Register 0x27 Remote 2 temperature = 0x01 default Register 0x77 Extended Resolution 2 = 0x00 default <7:6> TDM2, Remote 2 temperature LSBs <5:4> LTMP, local temperature LSBs <3:2> TDM1, Remote 1 temperature LSBs Temperature Measurement Limit Registers
High and low limit registers are associated with each temperature measurement channel. Exceeding the programmed high or low limit sets the appropriate status bit and can also generate SMBALERT interrupts. Register 0x4E Remote 1 temperature low limit = 0x01 default Register 0x4F Remote 1 temperature high limit = 0x7F default Register 0x50 local temperature low limit = 0x01 default Register 0x51 local temperature high limit = 0x7F default Register 0x52 Remote 2 temperature low limit = 0x01 default Register 0x53 Remote 2 temperature high limit = 0x7F default
D-
Figure 26. Measuring Temperature Using a PNP Transistor
Nulling Temperature Errors As CPUs run faster, it is more difficult to avoid high frequency clocks when routing the D+/D- traces around a system board. Even when recommended layout guidelines are followed, some temperature errors may still be attributed to noise coupled onto the D+/D- lines. Constant high frequency noise usually attenuates or increases temperature measurements by a linear, constant value. The ADT7467 has temperature offset registers at Address 0x70 and Address 0x72 for the Remote 1 and Remote 2 temperature channels, respectively. By performing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it using the offset registers. The offset registers automatically add an Offset 64/twos complement 8-bit reading to every temperature measurement. The LSBs add 0.5C offset to the temperature reading; therefore, the 8-bit register effectively allows temperature offsets of up to 64C with a resolution of 0.5C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Temperature Offset Registers Register 0x70 Remote 1 temperature offset = 0x00 (0C default) Register 0x71 local temperature offset = 0x00 (0C default) Register 0x72 Remote 2 temperature offset = 0x00 (0C default) ADT7460/ADT7467 Backwards-Compatible Mode By setting Bit 1 of Configuration Register 5 (0x7C), all temperature measurements are stored in the zone temperature value registers (Register 0x25, Register 0x26, and Register 0x27) in twos complement format in the range -128C to +127C. (The ADT7468 makes calculations based on the Offset 64 extended range and clamps the results if necessary.) The temperature limits must be reprogrammed in twos complement format. If a twos complement temperature below -63C is entered, the temperature is clamped to -63C. In this mode, the diode fault condition remains -128C = 1000 0000, whereas the fault condition is represented by -64C = 0000 0000 in the extended temperature range (-64C to +191C).
Reading Temperature from the ADT7467
It is important to note that temperature can be read from the ADT7467 as an 8-bit value (with 1C resolution) or as a 10-bit value (with 0.25C resolution). If only 1C resolution is required, the temperature readings can be read at any time and in no particular order. If the 10-bit measurement is required, this involves a 2-register read for each measurement. The extended resolution register (0x77) should be read first. Then all temperature reading registers freeze until all temperature reading registers are read. This prevents updating of an MSB reading while its two LSBs are read and vice versa.
ADDITIONAL ADC FUNCTIONS FOR TEMPERATURE MEASUREMENT
A number of other functions are available on the ADT7467 to offer the system designer increased flexibility.
Turn-Off Averaging
For each temperature measurement read from a value register, 16 readings are made internally, the results of which are averaged and then placed into the value register. Sometimes it is necessary to perform a very fast measurement. Setting Bit 4 of Configuration Register 2 (0x73) turns averaging off.
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ADT7467
Table 9. Conversion Time with Averaging Disabled
Channel Voltage Channels Remote Temperature 1 Remote Temperature 2 Local Temperature Measurement Time 0.7 ms 7 ms 7 ms 1.3 ms
TACH1 Minimum High Byte (0x55)
<7:5> selects ADC channel for single-channel convert mode
Overtemperature Events
Overtemperature events on a temperature channel can be automatically detected and dealt with in automatic fan speed control mode. Register 0x6A to Register 0x6C contain the THERM temperature limits. When a temperature exceeds its THERM temperature limit, all PWM outputs run at the maximum PWM duty cycle (0x38, 0x39, 0x3A); therefore, fans run at the fastest speed allowed and continue running at this speed until the temperature drops below THERM minus hysteresis. (This can be disabled by setting the BOOST bit in Configuration Register 3, Bit 2, Register 0x78.) The hysteresis value for that THERM temperature limit is the value programmed into Register 0x6D and Register 0x6E (hysteresis registers). The default hysteresis value is 4C.
THERM LIMIT
Table 10. Conversion Time with Averaging Enabled
Channel Voltage Channels Remote Temperature Local Temperature Measurement Time 11 ms 39 ms 12 ms
Single-Channel ADC Conversions
Setting Bit 6 of Configuration Register 2 (0x73) places the ADT7467 into single-channel ADC conversion mode. In this mode, users can read a single temperature channel only. The appropriate ADC channel is selected by writing to Bits <7:5> of the TACH1 minimum high byte register (0x55). Table 11. Channel Selection
Bits <7:5>, Register 0x55 101 110 111 Channel Selected Remote 1 temperature Local temperature Remote 2 temperature
HYSTERESIS (C) TEMPERATURE
Figure 27. THERM Temperature Limit Operation
Configuration Register 2 (0x73)
<4> = 1, averaging off <6> = 1, single-channel convert mode
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FANS
100%
ADT7467 LIMITS, STATUS REGISTERS, AND INTERRUPTS
LIMIT VALUES
High and low limits are associated with each measurement channel on the ADT7467. These limits form the basis of system-status monitoring in that a status bit can be set for any out-of-limit condition and detected by polling the device. Alternatively, SMBALERT interrupts can be generated to flag a processor or microcontroller of out-of-limit conditions. Register 0x58 TACH3 minimum low byte = 0xFF default Register 0x59 TACH3 minimum high byte = 0xFF default Register 0x5A TACH4 minimum low byte = 0xFF default Register 0x5B TACH4 minimum high byte = 0xFF default
Out-of-Limit Comparisons
Once all limits are programmed, the ADT7467 can be enabled for monitoring. The ADT7467 measures all voltage and temperature measurements in round-robin format and sets the appropriate status bit for out-of-limit conditions. TACH measurements are not part of this round-robin cycle. Comparisons are done differently, depending on whether the measured value is being compared to a high or low limit. High limit: > comparison performed Low limit: comparison performed Voltage and temperature channels use a window comparator for error detecting and, therefore, have high and low limits. Fan speed measurements use only a low limit. This fan limit is needed only in manual fan control mode.
8-Bit Limits
The following is a list of 8-bit limits on the ADT7467.
Voltage Limit Registers
Register 0x46 VCCP low limit = 0x00 default Register 0x47 VCCP high limit = 0xFF default Register 0x48 VCC low limit = 0x00 default Register 0x49 VCC high limit = 0xFF default
Temperature Limit Registers
Register 0x4E Remote 1 temperature low limit = 0x01 default Register 0x4F Remote 1 temperature high limit = 0x7F default Register 0x6A Remote 1 THERM temperature limit = 0xA4 default Register 0x50 local temperature low limit = 0x01 default Register 0x51 local temperature high limit = 0x7F default Register 0x6B local THERM temperature limit = 0xA4 default Register 0x52 Remote 2 temperature low limit = 0x01 default Register 0x53 Remote 2 temperature high limit = 0x7F default Register 0x6C Remote 2 THERM temperature limit = 0xA4 default
Analog Monitoring Cycle Time
The analog monitoring cycle begins when a 1 is written to the start bit (Bit 0) of Configuration Register 1 (0x40). By default, the ADT7463 powers up with this bit set. The ADC measures each analog input in turn and, as each measurement is completed, the result is automatically stored in the appropriate value register. This round-robin monitoring cycle continues unless disabled by writing a 0 to Bit 0 of Configuration Register 1. As the ADC is normally left to free-run in this manner, the time to monitor all analog inputs is normally not of interest because the most recently measured value of an input can be read at any time. For applications where the monitoring cycle time is important, it can be calculated easily. The total number of channels measured is * * * * One dedicated supply voltage input (VCCP) One supply voltage (VCC pin) One local temperature Two remote temperatures
THERM Limit Register
Register 0x7A THERM timer limit = 0x00 default
16-Bit Limits
The fan TACH measurements are 16-bit results. The fan TACH limits are also 16 bits, consisting of a high byte and low byte. Because slow or stalled fans are normally the only conditions of interest, only high limits exist for fan TACHs. Because the fan TACH period is measured, exceeding the limit indicates a slow or stalled fan.
Fan Limit Registers
Register 0x54 TACH1 minimum low byte = 0xFF default Register 0x55 TACH1 minimum high byte = 0xFF default Register 0x56 TACH2 minimum low byte = 0xFF default Register 0x57 TACH2 minimum high byte = 0xFF default
As mentioned previously, the ADC performs round-robin conversions. The total monitoring cycle time for averaged voltage and temperature monitoring is 145 ms. The total monitoring cycle time for voltage and temperature monitoring with averaging disabled is 19 ms. The ADT7467 is a derivative of the ADT7468. As a result, the total conversion time for the ADT7467 and ADT7468 are the same, even though the ADT7467 has less monitored channels.
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ADT7467
Fan TACH measurements are made in parallel and are not synchronized with the analog measurements in any way. Bit 5 (F4P) = 1 indicates Fan 4 has dropped below minimum speed. Alternatively, if the THERM function is used, it indicates that the THERM limit has been exceeded. Bit 4 (FAN3) = 1 indicates Fan 3 has dropped below minimum speed. Bit 3 (FAN2) = 1 indicates Fan 2 has dropped below minimum speed. Bit 2 (FAN1) = 1 indicates Fan 1 has dropped below minimum speed. Bit 1 (OVT) = 1 indicates a THERM overtemperature limit has been exceeded.
STATUS REGISTERS
The results of limit comparisons are stored in Interrupt Status Register 1 and Interrupt Status Register 2. The status register bit for each channel reflects the status of the last measurement and limit comparison on that channel. If a measurement is within limits, the corresponding status register bit is cleared to 0. If the measurement is out of limit, the corresponding status register bit is set to 1. The state of the various measurement channels can be polled by reading the status registers over the serial bus. In Bit 7 (OOL) of Interrupt Status Register 1 (0x41), 1 means that an out-of-limit event has been flagged in Interrupt Status Register 2. This means that the user also should read Interrupt Status Register 2. Alternatively, Pin 5 or Pin 9 can be configured as an SMBALERT output. This hardware interrupt automatically notifies the system supervisor of an out-of-limit condition. Reading the status registers clears the appropriate status bit if the error condition that caused the interrupt is absent. Status register bits are sticky. Whenever a status bit is set, indicating an out-of-limit condition, it remains set until read, even if the event that caused it is absent. The only way to clear the status bit is to read the status register after the event is absent. Interrupt mask registers (0x74 and 0x75) allow masking of individual interrupt sources to prevent an SMBALERT. However, if a masked interrupt source goes out of limit, its associated status bit is set in the interrupt status registers.
INTERRUPTS
SMBALERT Interrupt Behavior
The ADT7467 can be polled for status, or an SMBALERT interrupt can be generated for out-of-limit conditions. It is important to note how the SMBALERT output and status bits behave when writing interrupt handler software.
HIGH LIMIT
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT)
"STICKY" STATUS BIT TEMP BACK IN LIMIT (STATUS BIT STAYS SET)
SMBALERT
Figure 28. SMBALERT and Status Bit Behavior
Status Register 1 (0x41)
Bit 7 (OOL) = 1 denotes that a bit in Status Register 2 is set and that Status Register 2 should be read. Bit 6 (R2T) = 1 indicates that Remote 2 temperature high or low limit has been exceeded. Bit 5 (LT) = 1 indicates that local temperature high or low limit has been exceeded. Bit 4 (R1T) = 1 indicates that Remote 1 temperature high or low limit has been exceeded. Bit 2 (VCC) = 1 indicates that VCC high or low limit has been exceeded. Bit 1 (VCCP) = 1 indicates that VCCP high or low limit has been exceeded.
Figure 28 shows how the SMBALERT output and sticky status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition subsides and the status register is read. The status bits are referred to as sticky because they remain set until read by software. This ensures that an out-of-limit event cannot be missed if software is polling the device periodically. Note that the SMBALERT output remains low both for the duration that a reading is out of limit and until the status register has been read. This has implications on how software handles the interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up with servicing interrupts, it is recommend to handle the SMBALERT interrupt as follows: 1. 2. 3. Detect the SMBALERT assertion. Enter the interrupt handler. Read the status registers to identify the interrupt source.
Status Register 2 (0x42)
Bit 7 (D2) = 1 indicates an open or short on D2+/D2- inputs. Bit 6 (D1) = 1 indicates an open or short on D1+/D1- inputs.
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04498-022
ADT7467
4. Mask the interrupt source by setting the appropriate mask bit in the interrupt mask registers (Register 0x74 and Register 0x75). Take the appropriate action for a given interrupt source. Exit the interrupt handler. Periodically poll the status registers. If the interrupt status bit has cleared, reset the corresponding interrupt mask bit to 0. This causes the SMBALERT output and status bits to behave as shown in Figure 29. Bit 4 (FAN3) = 1 masks SMBALERT for Fan 3. Bit 3 (FAN2) = 1 masks SMBALERT for Fan 2. Bit 2 (FAN1) = 1 masks SMBALERT for Fan 1. Bit 1 (OVT) = 1 masks SMBALERT for overtemperature (exceeding THERM temperature limits).
5. 6. 7.
Enabling the SMBALERT Interrupt Output
The SMBALERT interrupt function is disabled by default. Pin 5 or Pin 9 can be reconfigured as an SMBALERT output to signal out-of-limit conditions. Table 12. Configuring Pin 5 as SMBALERT Output
HIGH LIMIT
TEMPERATURE
"STICKY" STATUS BIT
CLEARED ON READ (TEMP BELOW LIMIT) TEMP BACK IN LIMIT (STATUS BIT STAYS SET)
Register Configuration Register 3 (0x78)
Bit Setting <0> ALERT Enable = 1
Assigning THERM Functionality to a Pin
Pin 9 on the ADT7467 has four possible functions: SMBALERT, THERM, GPIO, and TACH4. The user chooses the required functionality by setting Bit 0 and Bit 1 of Configuration Register 4 at Address 0x7D. Table 13. Configuring Pin 9
Bit 1 0 0 1 1 Bit 0 0 1 0 1 Function TACH4 THERM SMBALERT GPIO
SMBALERT
INTERRUPT MASK BIT SET
Figure 29. Effect of Masking the Interrupt Source on SMBALERT Output
Masking Interrupt Sources
Interrupt Mask Registers 1 and 2 are located at Address 0x74 and Address 0x75, respectively, and allow individual interrupt sources to be masked to prevent SMBALERT interrupts. Note that masking an interrupt source prevents only the SMBALERT output from being asserted; the appropriate status bit is set normally.
04498-023
INTERRUPT MASK BIT CLEARED (SMBALERT REARMED)
Once Pin 9 is configured as THERM, it must be enabled (Bit 1, Configuration Register 3 at Address 0x78).
Interrupt Mask Register 1 (0x74)
Bit 7 (OOL) = 1 masks SMBALERT for any alert condition flagged in Interrupt Status Register 2. Bit 6 (R2T) = 1 masks SMBALERT for Remote 2 temperature channel. Bit 5 (LT) = 1 masks SMBALERT for local temperature channel. Bit 4 (R1T) = 1 masks SMBALERT for Remote 1 temperature channel. Bit 2 (VCC) = 1 masks SMBALERT for VCC channel. Bit 0 (VCCP) = 1 masks SMBALERT for VCCP channel.
THERM as an Input
When THERM is configured as an input, the user can time assertions on the THERM pin. This can be useful for connecting to the PROCHOT output of a CPU to gauge system performance. The user can also set up the ADT7467 so that when the THERM pin is driven low externally, the fans run at 100%. The fans run at 100% for the duration of the time that the THERM pin is pulled low. This is done by setting the BOOST bit (Bit 2) in Configuration Register 3 (0x78) to 1. This only works if the fan is already running, for example, in manual mode when the current duty cycle is above 0x00, or in automatic mode when the temperature is above TMIN. If the temperature is below TMIN or if the duty cycle in manual mode is set to 0x00, externally pulling THERM low has no effect. See Figure 30 for more information.
Interrupt Mask Register 2 (0x75)
Bit 7 (D2) = 1 masks SMBALERT for Diode 2 errors. Bit 6 (D1) = 1 masks SMBALERT for Diode 1 errors. Bit 5 (F4P) = 1 masks SMBALERT for Fan 4 failure. If the TACH4 pin is used as the THERM input, this bit masks SMBALERT for a THERM event.
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ADT7467
TMIN
It is important to be aware of the following when using the THERM timer. After a THERM timer is read (Register 0x79), the following occurs:
THERM
* *
The contents of the timer are cleared upon a read. The F4P bit (Bit 5) of Interrupt Status Register 2 must be cleared, assuming that the THERM timer limit has been exceeded.
THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100% BECAUSE TEMPERATURE IS BELOW TMIN
04498-024
If the THERM timer is read during a THERM assertion, the following occurs: * * * * The contents of the timer are cleared. Bit 0 of the THERM timer is set to 1 because a THERM assertion is occurring. The THERM timer increments from 0. If the THERM timer limit (Register 0x7A) is 0x00, the F4P bit is set.
THERM
THERM ASSERTED TO LOW AS AN INPUT: FANS DO NOT GO TO 100% BECAUSE TEMPERATURE IS ABOVE TMIN AND FANS ARE ALREADY RUNNING
Figure 30. Asserting THERM Low as an Input in Automatic Fan Speed Control Mode
THERM Timer
The ADT7467 has an internal timer to measure THERM assertion time. For example, the THERM input can be connected to the PROCHOT output of a Pentium 4 CPU to measure system performance. The THERM input can also be connected to the output of a trip point temperature sensor. The timer is started on the assertion of the THERM input and stopped when THERM is deasserted. The timer counts THERM times cumulatively, that is, the timer resumes counting on the next THERM assertion. The THERM timer continues to accumulate THERM assertion times until the timer is read (it is cleared upon a read) or until it reaches full scale. If the counter reaches full scale, it stops at that reading until cleared. The 8-bit THERM timer register (0x79) is designed such that Bit 0 is set to 1 upon the first THERM assertion. Once the cumulative THERM assertion time exceeds 45.52 ms, Bit 1 of the THERM timer is set and Bit 0 becomes the LSB of the timer with a resolution of 22.76 ms (see Figure 31).
THERM TIMER (REG. 0x79)
00000001 76543210
THERM ASSERTED 22.76ms
THERM
ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 00000010 76543210
THERM ASSERTED 45.52ms
THERM
ACCUMULATE THERM LOW ASSERTION TIMES THERM TIMER (REG. 0x79) 00000101 7 6 5 4 3 2 1 0 THERM ASSERTED 113.8ms (91.04ms + 22.76ms)
Figure 31.Understanding the THERM Timer
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04498-025
ADT7467
Generating SMBALERT Interrupts From THERM Timer Events
The ADT7467 can generate SMBALERTs when a programmable THERM timer limit has been exceeded. This allows the system designer to ignore brief, infrequent THERM assertions while capturing longer THERM timer events. Register 0x7A is the THERM timer limit register. This 8-bit register allows a limit from 0 sec (first THERM assertion) to 5.825 sec to be set before an SMBALERT is generated. The THERM timer value is compared with the contents of the THERM timer limit register. If the THERM timer value exceeds the THERM timer limit,
2.914s 1.457s 728.32ms 364.16ms 182.08ms 91.04ms 45.52ms 22.76ms
the F4P bit (Bit 5) of Interrupt Status Register 2 is set and an SMBALERT is generated. Note that the F4P bit (Bit 5) of Interrupt Mask Register 2 (0x75) masks SMBALERT if this bit is set to 1; however, the F4P bit of Interrupt Status Register 2 remains set if the THERM timer limit is exceeded. Figure 32 is a functional block diagram of the THERM timer, limit, and associated circuitry. Writing a value of 0x00 to the THERM timer limit register (0x7A) causes SMBALERT to be generated upon the first THERM assertion. A THERM timer limit value of 0x01 generates an SMBALERT once cumulative THERM assertions exceed 45.52 ms.
2.914s 1.457s 728.32ms 364.16ms THERM TIMER (REG. 0x79) 182.08ms 91.04ms 45.52ms 22.76ms
THERM LIMIT (REG. 0x7A)
01234567
76543210
THERM THERM TIMER CLEARED ON READ
COMPARATOR
IN
OUT LATCH RESET
F4P BIT (BIT 5) STATUS REGISTER 2
SMBALERT
CLEARED ON READ
1 = MASK
04498-026
F4P BIT (BIT 5) INTERRUPT MASK REGISTER 2 (REG. 0x75)
Figure 32. Functional Block Diagram of THERM Monitoring Circuitry
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ADT7467
Configuring THERM Behavior
1. Configure the relevant pin as the THERM timer input. Setting Bit 1 (THERM timer enable) of Configuration Register 3 (0x78) enables the THERM timer monitoring functionality. This is disabled on Pin 9 by default. Setting Bit 0 and Bit 1 (Pin 9 Func) of Configuration Register 4 (0x7D) enables THERM timer/output functionality on Pin 9 (Bit 1, THERM, of Configuration Register 3 must also be set). Pin 9 can also be used as TACH4. 2. Select the desired fan behavior for THERM timer events. Assuming that the fans are running, setting Bit 2 (BOOST bit) of Configuration Register 3 (0x78) causes all fans to run at 100% duty cycle whenever THERM is asserted. This allows fail-safe system cooling. If this bit is 0, the fans run at their current settings and are not affected by THERM events. If the fans are not already running when THERM is asserted, the fans do not run to full speed. 3. Select whether THERM timer events should generate SMBALERT interrupts. When set, Bit 5 (F4P) of Mask Register 2 (0x75) masks SMBALERTs when the THERM timer limit value is exceeded. This bit should be cleared if SMBALERT based on THERM events are required. 4. Select a suitable THERM limit value. This value determines whether an SMBALERT is generated upon the first THERM assertion, or if only a cumulative THERM assertion time limit is exceeded. A value of 0x00 causes an SMBALERT to be generated upon the first THERM assertion. 5. Select a THERM monitoring time. This value specifies how often OS or BIOS level software checks the THERM timer. For example, BIOS could read the THERM timer once an hour to determine the cumulative THERM assertion time. If, for example, the total THERM assertion time is <22.76 ms in Hour 1, >182.08 ms in Hour 2, and >2.914 sec in Hour 3, this can indicate that system performance is degrading significantly, because THERM is asserting more frequently on an hourly basis. Alternatively, OS or BIOS level software can timestamp when the system is powered on. If an SMBALERT is generated because the THERM timer limit has been exceeded, another timestamp can be taken. The difference in time can be calculated for a fixed THERM timer limit. For example, if it takes one week for a THERM timer limit of 2.914 sec to be exceeded and the next time it takes only 1 hour, this is an indication of a serious degradation in system performance.
Configuring the THERM Pin as an Output
In addition to monitoring THERM as an input, the ADT7467 can optionally drive THERM low as an output. In cases where PROCHOT is bidirectional, THERM can be used to throttle the processor by asserting PROCHOT. The user can preprogram system-critical thermal limits. If the temperature exceeds a thermal limit by 0.25C, THERM asserts low. If the temperature is still above the thermal limit on the next monitoring cycle, THERM stays low. THERM remains asserted low until the temperature is equal to or below the thermal limit. Because the temperature for that channel is measured only once for every monitoring cycle, it is guaranteed to remain low for at least one monitoring cycle after THERM is asserted. The THERM pin can be configured to assert low if the Remote 1, local, or Remote 2 THERM temperature limits are exceeded by 0.25C. The THERM temperature limit registers are at Register 0x6A, Register 0x6B, and Register 0x6C, respectively. Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61 enables the THERM output feature for the Remote 1, local, and Remote 2 temperature channels, respectively. Figure 33 shows how the THERM pin asserts low as an output in the event of a critical overtemperature.
THERM LIMIT +0.25C THERM LIMIT
TEMP
THERM
Figure 33. Asserting THERM as an Output, Based on Tripping THERM Limits
An alternative method of disabling THERM is to program the THERM temperature limit to -64C or less in Offset 64 mode, or to -128C or less in twos complement mode; therefore, for THERM temperature limit values less than -64C or -128C, respectively, THERM is disabled.
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04498-027
ADT7467 MONITORING CYCLE
ADT7467 ACTIVE COOLING
DRIVING THE FAN USING PWM CONTROL
The ADT7467 uses pulse-width modulation (PWM) to control fan speed. This relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The external circuitry required to drive a fan using PWM control is extremely simple. For 4-wire fans, the PWM drive may need only a pull-up resistor. In many cases, the 4-wire fan PWM input has a built-in pull-up resistor. The ADT7467 PWM frequency can be set to a selection of low frequencies or a single high PWM frequency. The low frequency options are usually used for 2-wire and 3-wire fans, and the high frequency option is usually used for 4-wire fans. For 2-wire or 3-wire fans, a single N-channel MOSFET is the only drive device required. The specifications of the MOSFET depend on the maximum current required by the fan being driven. Typical notebook fans draw a nominal 170 mA; therefore, SOT devices can be used where board space is a concern. In desktops, fans can typically draw 250 mA to 300 mA each. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET have a gate voltage drive of VGS < 3.3 V for direct interfacing to the PWMx pin. VGS can be greater than 3.3 V as long as the pull-up on the gate is tied to 5 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET, which would reduce the voltage applied across the fan and, therefore, the maximum operating speed of the fan. Figure 34 shows how to drive a 3-wire fan using PWM control.
12V 10k TACHx 10k 4.7k 3.3V 12V FAN 1N4148 12V
pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section. Figure 35 shows a fan drive circuit using an NPN transistor such as a general-purpose MMBT2222. Although these devices are inexpensive, they tend to have much lower current handling capabilities and higher on resistance than MOSFETs. When choosing a transistor, care should be taken to ensure that it meets the fan's current requirements. Ensure that the base resistor is chosen such that the transistor is saturated when the fan is powered on. Because 4-wire fans are powered continuously, the fan speed is not switched on or off as with previous PWM driven/powered fans. This enables it to perform better than 3-wire fans, especially for high frequency applications. Figure 36 shows a typical drive circuit for 4-wire fans.
12V 10k TACHx 10k 4.7k 3.3V TACH 12V FAN 1N4148 12V
ADT7467
665 PWMx Q1 MMBT2222
04498-029
Figure 35. Driving a 3-Wire Fan Using an NPN Transistor
12V 12V 12V, 4-WIRE FAN 10k TACHx 10k 4.7k 3.3V TACH VCC TACH PWM
ADT7467
2k
04498-041
ADT7467
10k PWMx Q1 NDT3055L
04498-028
PWMx
Figure 36. Driving a 4-Wire Fan
Figure 34. Driving a 3-Wire Fan Using an N-Channel MOSFET
Driving Two Fans from PWM3
The ADT7467 has four TACH inputs available for fan speed measurement, but only three PWM drive outputs. If a fourth fan is used in the system, it should be driven from the PWM3 output in parallel with the third fan. Figure 37 shows how to drive two fans in parallel using low cost NPN transistors. Figure 38 shows the equivalent circuit using a MOSFET.
Figure 34 uses a 10 k pull-up resistor for the TACH signal. This assumes that the TACH signal is an open-collector from the fan. In all cases, the TACH signal from the fan must be kept below 5 V maximum to prevent damaging the ADT7467. If in doubt as to whether the fan used has an open-collector or totem
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ADT7467
12V
ADT7467
3.3V
3.3V TACH3
1N4148
TACH4
1k PWM3 2.2k Q1 MMBT3904 10
Q2 MMBT2222
10
04498-030
Q3 MMBT2222
Figure 37. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors
3.3V 10k TYPICAL TACH4 3.3V +V +V
ADT7467
TACH3
10k TYPICAL 3.3V TACH 5V OR 12V FAN
1N4148 TACH
5V OR 12V FAN
10k TYPICAL
04498-031
PWM3
Q1 NDT3055L
Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET
Because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 5 mA maximum current specified on the data sheet.
Driving 2-Wire Fans
The ADT7467 can only support 2-wire fans when low frequency PWM mode is selected in Configuration Register 5, Bit 2. If this bit is not set to 1, the ADT7467 cannot measure the speed of 2-wire fans. Figure 39 shows how a 2-wire fan can be connected to the ADT7467. This circuit allows the speed of a 2-wire fan to be measured, even though the fan has no dedicated TACH signal. A series resistor, RSENSE, in the fan circuit converts the fan commutation pulses into a voltage, which is ac-coupled into the ADT7467 through the 0.01 F capacitor. On-chip signal conditioning allows accurate monitoring of fan speed. The value of RSENSE depends on the programmed input threshold and the current drawn by the fan. For fans drawing approximately 200 mA, a 2 RSENSE value is suitable when the threshold is programmed as 40 mV. For fans that draw more current, such as larger desktop or server fans, RSENSE can be reduced for the same programmed threshold. The smaller the threshold programmed, the better, because more voltage is developed across the fan and the fan spins faster. Figure 40 shows a typical plot of the sensing waveform at the TACHx pin.
Driving up to Three Fans from PWM3
TACH measurements for fans are synchronized to particular PWM channels; for example, TACH1 is synchronized to PWM1. TACH3 and TACH4 are both synchronized to PWM3; therefore, PWM3 can drive two fans. Alternatively, PWM3 can be programmed to synchronize TACH2, TACH3, and TACH4 to the PWM3 output. This allows PWM3 to drive two or three fans. In this case, the drive circuitry is as shown in Figure 37 and Figure 38. The SYNC bit in Register 0x62 enables this function. Synchronization is not required in high frequency mode when used with 4-wire fans.
<4> (SYNC) Enhanced Acoustics Register 1 (0x62)
SYNC = 1 synchronizes TACH2, TACH3, and TACH4 to PWM3.
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ADT7467
Note that when the voltage spikes (either negative going or positive going) are more than 40 mV in amplitude, the fan speed can be reliably determined.
+V
TACH Inputs
When configured as TACH inputs, Pin 4, Pin 6, Pin 7, and Pin 9 are open-drain TACH inputs intended for fan speed measurement. Signal conditioning in the ADT7467 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even when VCC is less than 5 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 42 to Figure 45 show circuits for most common fan TACH outputs. If the fan TACH output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 42.
VCC 12V PULL-UP 4.7k TYPICAL
ADT7467
3.3V
5V OR 12V FAN
1N4148
10k TYPICAL PWMx Q1 NDT3055L
0.01F
04498-032
TACHx
RSENSE 2 TYPICAL
Figure 39. Driving a 2-Wire Fan
TACH OUTPUT TACHx
FAN SPEED COUNTER
04498-034
ADT7467
Figure 42. Fan with TACH Pull-Up to VCC
If the fan output has a resistive pull-up to 12 V (or another voltage that is greater than 5 V), the fan output can be clamped with a Zener diode, as shown in Figure 43. The Zener diode voltage should be chosen so that it is greater than the VIH of the TACH input but less than 5 V, allowing for the voltage tolerance of the Zener. A value between 3 V and 5 V is suitable.
04498-033
12V
VCC
Figure 40. Fan Speed Sensing Waveform at TACHx Pin
LAYING OUT 2-WIRE AND 3-WIRE FANS
Figure 41 shows how to lay out a common circuit arrangement for 2-wire and 3-wire fans. Some components are not populated, depending on whether a 2-wire or 3-wire fan is used.
12V OR 5V R1 1N4148 3.3V OR 5V R2 R5 PWM C1 TACH R3 Q1 MMBT2222 R4 FOR 3-WIRE FANS: POPULATE R1, R2, R3 R4 = 0 C1 = UNPOPULATED
04498-042
PULL-UP 4.7k TYPICAL
TACH OUTPUT TACHx ZD1*
FAN SPEED COUNTER
04498-035 04498-036
ADT7467
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC.
Figure 43. Fan with TACH Pull-Up to a Voltage >5 V (For Example, 12 V), Clamped with Zener Diode
If the fan has a strong pull-up (less than 1 k) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 44.
5V OR 12V FAN PULL-UP TYP <1k OR TOTEM POLE VCC
R1 10k TACH OUTPUT
TACHx ZD1 ZENER*
FAN SPEED COUNTER
FOR 2-WIRE FANS: POPULATE R4, C1 R1, R2, R3 UNPOPULATED R4 = 2
ADT7467
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC.
Figure 41. Planning for 2-Wire or 3-Wire Fans on a PCB
Figure 44. Fan with Strong TACH Pull-Up to >VCC or Totem-Pole Output,
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ADT7467
Clamped with Zener and Resistor
Fan Speed Measurement Registers
The fan tachometer readings are 16-bit values consisting of a 2-byte read from the ADT7467. Register 0x28 TACH1 low byte = 0x00 default Register 0x29 TACH1 high byte = 0x00 default Register 0x2A TACH2 low byte = 0x00 default Register 0x2B TACH2 high byte = 0x00 default Register 0x2C TACH3 low byte = 0x00 default Register 0x2D TACH3 high byte = 0x00 default Register 0x2E TACH4 low byte = 0x00 default Register 0x2F TACH4 high byte = 0x00 default
Alternatively, a resistive attenuator can be used, as shown in Figure 45. R1 and R2 should be chosen such that 2 V < VPULL-UP x R2/(RPULL-UP + R1 + R2) < 5 V The fan inputs have an input resistance of nominally 160 k to ground, which should be taken into account when calculating resistor values. With a pull-up voltage of 12 V and a pull-up resistor of less than 1 k, suitable values for R1 and R2 are 100 k and 47 k, respectively. This gives a high input voltage of 3.83 V.
12V VCC
<1k
R1* TACH OUTPUT
TACHx R2*
Reading Fan Speed from the ADT7467
FAN SPEED COUNTER
04498-037
ADT7467
*SEE TEXT.
Figure 45. Fan with Strong TACH Pull-Up to >VCC or Totem-Pole Output, Attenuated with R1/R2
FAN SPEED MEASUREMENT
The fan counter does not count the fan TACH output pulses directly, because the fan speed could be less than 1000 RPM, and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (see Figure 46); therefore, the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. The number of pulses counted, N, is determined by the settings of Register 0x7B (TACH pulses per revolution register). This register contains two bits for each fan, allowing counting of one, two (default), three, or four TACH pulses.
CLOCK
The measurement of fan speeds involves a 2-register read for each measurement. The low byte should be read first. This freezes the high byte until both high and low byte registers are read, preventing erroneous TACH readings. The fan tachometer reading registers report the number of 11.11 s period clocks (90 kHz oscillator) gated to the fan speed counter from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse, assuming two pulses per revolution are being counted. Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan runs. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or is running very slowly (<100 RPM). High limit > comparison performed Because the actual fan TACH period is being measured, falling below a fan TACH limit by 1 sets the appropriate status bit and can be used to generate an SMBALERT.
Fan TACH Limit Registers
The fan TACH limit registers are 16-bit values consisting of two bytes. Register 0x54 TACH1 minimum low byte = 0xFF default Register 0x55 TACH1 minimum high byte = 0xFF default
PWM
Register 0x56 TACH2 minimum low byte = 0xFF default
1 2
04498-038
TACH
Register 0x57 TACH2 minimum high byte = 0xFF default Register 0x58 TACH3 minimum low byte = 0xFF default
3 4
Register 0x59 TACH3 minimum high byte = 0xFF default Register 0x5A TACH4 minimum low byte = 0xFF default Register 0x5B TACH4 minimum high byte = 0xFF default
Figure 46. Fan Speed Measurement
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ADT7467
Fan Speed Measurement Rate
The fan TACH readings are normally updated once every second. When set, the FAST bit (Bit 3) of Configuration Register 3 (0x78) updates the fan TACH readings every 250 ms. If a fan is powered directly from 5 V or 12 V and is not driven by a PWM channel, its associated dc bit in Configuration Register 3 should be set. This allows TACH readings to be taken on a continuous basis for fans connected directly to a dc source. For optimal results, the associated dc bit should always be set when using 4-wire fans.
2-Wire Fan Speed Measurements (Low Frequency Mode Only)
The ADT7467 is capable of measuring the speed of 2-wire fans, that is, fans without TACH outputs. To do this, the fan must be interfaced as shown in the Driving 2-Wire Fans section. In this case, the TACH inputs should be reprogrammed as analog inputs, AIN.
Configuration Register 2 (0x73)
Bit 3 (AIN4) = 1, Pin 9 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 2 (AIN3) = 1, Pin 4 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 1 (AIN2) = 1, Pin 7 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor. Bit 0 (AIN1) = 1, Pin 6 is reconfigured to measure the speed of a 2-wire fan using an external sensing resistor and coupling capacitor.
Calculating Fan Speed
Assuming a fan with two pulses per revolution (and two pulses per revolution being measured), fan speed is calculated by Fan Speed (RPM) = (90,000 x 60)/Fan TACH Reading where Fan TACH Reading is the 16-bit fan tachometer reading.
Example TACH1 high byte (Register 0x29) = 0x17 TACH1 low byte (Register 0x28) = 0xFF
What is Fan 1 speed in RPM? Fan 1 TACH Reading = 0x17FF = 6143 (decimal) RPM = (f x 60)/Fan 1 TACH Reading RPM = (90,000 x 60)/6143 Fan Speed = 879 RPM
AIN Switching Threshold
Having configured the TACH inputs as AIN inputs for 2-wire measurements, a user can select the sensing threshold for the AIN signal.
Configuration Register 4 (0x7D)
<3:2> AINL, input threshold for 2-wire fan speed measurements 00 = 20 mV 01 = 40 mV 10 = 80 mV 11 = 130 mV
Fan Pulses per Revolution
Different fan models can output either one, two, three, or four TACH pulses per revolution. Once the number of fan TACH pulses has been determined, it can be programmed into the fan pulses per revolution register (0x7B) for each fan. Alternatively, this register can be used to determine the number of pulses per revolution output for a given fan. By plotting fan speed measurements at 100% speed with different pulses per revolution setting, the smoothest graph with the lowest ripple determines the correct pulses per revolution value.
FAN SPIN-UP
The ADT7467 has a unique fan spin-up function. It spins the fan at 100% PWM duty cycle until two TACH pulses are detected on the TACH input. Then, the PWM duty cycle goes to the expected running value, for example, 33%. The advantage is that fans have different spin-up characteristics and take different times to overcome inertia. The ADT7467 runs the fans just fast enough to overcome inertia and is quieter during spin-up than other fans programmed to spin up for a given spin-up time.
Fan Pulses per Revolution Register
<1:0> Fan 1 default = 2 pulses per revolution <3:2> Fan 2 default = 2 pulses per revolution <5:4> Fan 3 default = 2 pulses per revolution <7:6> Fan 4 default = 2 pulses per revolution 00 = 1 pulse per revolution 01 = 2 pulses per revolution 10 = 3 pulses per revolution 11 = 4 pulses per revolution
Fan Start-Up Timeout
To prevent the generation of false interrupts as a fan spins up (because it is below running speed), the ADT7467 includes a fan start-up timeout function. During this time, the ADT7467 looks for two TACH pulses. If two TACH pulses are not detected, an interrupt is generated. Using Configuration Register 1 (0x40)
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ADT7467
Bit 5 (FSPDIS), the functionality of this bit can be changed (see the Disabling Fan Start-Up Timeout section).
PWM LOGIC STATE
The PWM outputs can be programmed high for 100% duty cycle (noninverted) or programmed low for 100% duty cycle (inverted).
PWM1 Configuration Register (0x5C)
<2:0> SPIN, start-up timeout for PWM1 000 = no start-up timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec
PWM1 Configuration Register (0x5C)
<4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle
PWM2 Configuration Register (0x5D)
<4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle
PWM2 Configuration Register (0x5D)
<2:0> SPIN, start-up timeout for PWM2 000 = no start-up timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec
PWM3 Configuration Register (0x5E)
<4> INV 0 = logic high for 100% PWM duty cycle 1 = logic low for 100% PWM duty cycle
Low Frequency Mode PWM Drive Frequency
The PWM drive frequency can be adjusted for the application. Register 0x5F to Register 0x61 configure the PWM frequency for PWM1 to PWM3, respectively. In high frequency mode, the PWM drive frequency is 22.5 kHz and cannot be changed.
PWM1 Frequency Registers (0x5F to 0x61)
<2:0> FREQ 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz default 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz
PWM3 Configuration Register (0x5E)
<2:0> SPIN, start-up timeout for PWM3 000 = no start-up timeout 001 = 100 ms 010 = 250 ms default 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec
Disabling Fan Start-Up Timeout
Although a fan startup makes fan spin-ups more quiet than fixed-time spin-ups, users can use fixed spin-up times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1 (0x40) disables the spin-up for two TACH pulses, and the fan spins up for the fixed time selected in Register 0x5C to Register 0x5E.
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ADT7467
FAN SPEED CONTROL
The ADT7467 controls fan speed using two modes: automatic and manual. In automatic fan speed control mode, fan speed is varied with temperature without CPU intervention once initial parameters are set up. The advantage of this is that if the system hangs, it is guaranteed that the system is protected from overheating. The automatic fan speed control incorporates a feature called dynamic TMIN calibration. This feature reduces the design effort required to program the automatic fan speed control loop. For information on programming the automatic fan speed control loop and the dynamic TMIN calibration, see the Automatic Fan Control Overview section. In manual fan speed control mode, the ADT7467 allows the duty cycle of any PWM output to be manually adjusted. This can be useful if the user wants to change fan speed in software or adjust PWM duty cycle output for test purposes. Bits <7:5> of Register 0x5C to Register 0x5E (PWM Configuration) control the behavior of each PWM output.
Programming the PWM Current Duty Cycle Registers
The PWM current duty cycle registers are 8-bit registers that allow the PWM duty cycle for each output to be set anywhere from 0% to 100% in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39 Example 1: For a PWM duty cycle of 50%, Value (decimal) = 50/0.39 = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal) Example 2: For a PWM duty cycle of 33%, Value (decimal) = 33/0.39 = 85 (decimal) Value = 85 (decimal) or 0x54 (hexadecimal)
PWM Current Duty Cycle Registers
Register 0x30 PWM1 current duty cycle = 0x00 (0% default) Register 0x31 PWM2 current duty cycle = 0x00 (0% default) Register 0x32 PWM3 current duty cycle = 0x00 (0% default) By reading the PWMx current duty cycle registers, the user can keep track of the current duty cycle on each PWM output even when the fans are running in automatic fan speed control mode or acoustic enhancement mode. See the Automatic Fan Control Overview section for details.
PWM Configuration Register (0x5C to 0x5E)
<7:5> BHVR 111 = manual mode In manual fan speed control mode, each PWM output can be manually updated by writing to Register 0x30 through Register 0x32 (PWMx current duty cycle registers).
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ADT7467 MISCELLANEOUS FUNCTIONS
OPERATING FROM 3.3 V STANDBY
The ADT7467 has been specifically designed to operate from a 3.3 V STANDBY supply. In computers that support S3 and S5 states, the core voltage of the processor is lowered in these states. If using the dynamic TMIN mode, lowering the core voltage of the processor changes the CPU temperature and changes the dynamics of the system under dynamic TMIN control. Likewise, when monitoring THERM, the THERM timer should be disabled during these states.
POWER-ON DEFAULT
When the ADT7467 is powered up, it polls the VCCP input. If VCCP stays below 0.75 V (the system CPU power rail is not powered up), the ADT7467 assumes the functionality of the default registers after the ADT7467 is addressed via any valid SMBus transaction. If VCC goes high (the system processor power rail is powered up), a fail-safe timer begins to count down. If the ADT7467 is not addressed by a valid SMBus transaction before the fail-safe timeout (4.6 sec) lapses, the ADT7467 drives the fans to full speed. If the ADT7467 is addressed by a valid SMBus transaction after this point, the fans stop and the ADT7467 assumes its default settings and begins normal operation. If VCCP goes high (the system processor power rail is powered up), a fail-safe timer begins to count down. If the ADT7467 is addressed by a valid SMBus transaction before the fail-safe timeout (4.6 sec) lapses, the ADT7467 operates normally, assuming the functionality of all default registers. See the flow chart in Figure 48.
ADT7467 IS POWERED UP
Dynamic TMIN Control Register 1 (0x36) <1> VCCPLO = 1
When the power is supplied from 3.3 V STANDBY and the VCCP voltage drops below the VCCP low limit, the following occurs: 1. 2. 3. 4. 5. Status Bit 1 (VCCP) in Interrupt Status Register 1 is set. SMBALERT is generated if enabled. THERM monitoring is disabled. The THERM timer should hold its value prior to the S3 or S5 state. Dynamic TMIN control is disabled. This prevents TMIN from being adjusted due to an S3 or S5 state. The ADT7467 is prevented from shutting down.
Once the core voltage, VCCP, goes above the VCCP low limit, everything is re-enabled and the system resumes normal operation.
Y
HAS THE ADT7467 BEEN ACCESSED BY A VALID SMBUS TRANSACTION? N IS VCCP ABOVE 0.75V? Y START FAIL-SAFE TIMER CHECK V CCP
XNOR TREE TEST MODE
The ADT7467 includes an XNOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XNOR tree, it is possible to detect opens or shorts on the system board. Figure 47 shows the signals that are exercised in the XNOR tree test mode. The XNOR tree test is invoked by setting Bit 0 (XEN) of the XNOR tree test enable register (0x6F).
TACH1 TACH2 Y
N
HAS THE ADT7467 BEEN ACCESSED BY A VALID SMBUS TRANSACTION? N FAIL-SAFE TIMER ELAPSES AFTER THE FAIL-SAFE TIMEOUT
TACH3
HAS THE ADT7467 BEEN ACCESSED BY A VALID SMBUS TRANSACTION? Y
N
RUN THE FANS TO FULL SPEED
TACH4
PWM2
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HAS THE ADT7467 BEEN ACCESSED BY A VALID SMBUS TRANSACTION? Y START UP THE ADT7467 NORMALLY SWITCH OFF FANS
N
PWM3
PWM1/XTO
Figure 47. XNOR Tree Test
Figure 48. Power-On Flowchart
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ADT7467 AUTOMATIC FAN CONTROL OVERVIEW
The ADT7467 can automatically control the speed of fans based on the measured temperature. This is done independently of CPU intervention once initial parameters are set up. The ADT7467 has a local temperature sensor and two remote temperature channels that can be connected to a CPU on-chip thermal diode (available on Intel Pentium class and other CPUs). These three temperature channels can be used as the basis for automatic fan speed control to drive fans using pulsewidth modulation (PWM). Automatic fan speed control reduces acoustic noise by optimizing fan speed according to accurately measured temperature. Reducing fan speed can also decrease system current consumption. The automatic fan speed control mode is very flexible due to the number of programmable parameters, including TMIN and TRANGE. The TMIN and TRANGE values for a temperature channel and, therefore, for a given fan are critical because they define the thermal characteristics of the system. Thermal validation of the system is one of the most important steps in the design process; therefore, these values should be selected carefully. Figure 49 shows a top-level overview of the automatic fan control circuitry on the ADT7467. From a systems-level perspective, up to three system temperatures can be monitored and used to control three PWM outputs. The three PWM outputs can be used to control up to four fans. The ADT7467 allows the speed of four fans to be monitored. Each temperature channel has a thermal calibration block, allowing the designer to individually configure the thermal characteristics of each temperature channel. For example, one can decide to run the CPU fan when CPU temperature increases above 60C and to run a chassis fan when the local temperature increases above 45C. At this stage, the designer has not assigned these thermal calibration settings to a particular fan drive (PWM) channel. The right side of Figure 49 shows controls that are fan-specific. The designer can individually control parameters such as minimum PWM duty cycle, fan speed failure thresholds, and even ramp control of the PWM outputs. Therefore, automatic fan control ultimately allows gracefully changing fan speed so that it is less perceptible to the system user.
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
REMOTE 1 TEMP
TMIN
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
LOCAL TEMP
TMIN
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
PWM3
REMOTE 2 TEMP
TMIN
TRANGE
Figure 49. Automatic Fan Control Block Diagram
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0%
TACH3
ADT7467
DYNAMIC TMIN CONTROL MODE
In addition to the automatic fan speed control mode, the ADT7467 has a mode that extends the basic automatic fan speed control loop. Dynamic TMIN control allows the ADT7467 to intelligently adapt the system's cooling solution to optimize system performance or system acoustics, depending on user or design requirements. Use of dynamic TMIN control alleviates the need to design for worst-case conditions, and it significantly reduces the time required for system design and validation.
VENTS FAN VENTS I/O CARDS POWER SUPPLY CPU FAN I/O CARDS POWER SUPPLY
GOOD CPU AIRFLOW
CPU
POOR CPU AIRFLOW
FAN VENTS
DRIVE BAYS
DRIVE BAYS
Designing for Worst-Case Conditions
System design must always allow for worst-case conditions. In PC design, the worst-case conditions include, but are not limited to, the following: * Worst-Case Altitude A computer can be operated at different altitudes. The altitude affects the relative air density, which alters the effectiveness of the fan cooling solution. For example, comparing 40C air temperature at 10,000 ft. to 20C air temperature at sea level, relative air density is increased by 40%. This means that at a given temperature, the fan can spin 40% slower and make less noise at sea level than it can at 10,000 ft. Worst-Case Fan Due to manufacturing tolerances, fan speeds in RPM are normally quoted with a tolerance of 20%. The designer should assume that the fan RPM is 20% below tolerance. This translates to reduced system airflow and elevated system temperature. Note that a difference of 20% in the fans' tolerance can negatively impact system acoustics because the fans run faster and generate more noise. Worst-Case Chassis Airflow The same motherboard can be used in a number of different chassis configurations. The design of the chassis and the physical location of fans and components determine the system thermal characteristics. Moreover, for a given chassis, the addition of add-in cards, cables, and other system configuration options can alter the system airflow and reduce the effectiveness of the system cooling solution. The cooling solution can also be inadvertently altered by the end user. (For example, placing a computer against a wall can block the air ducts and reduce system airflow.) *
GOOD VENTING = GOOD AIR EXCHANGE
POOR VENTING = POOR AIR EXCHANGE
Figure 50. Chassis Airflow Issues
Worst-Case Processor Power Consumption Designing for worst-case CPU power consumption can result in a processor becoming overcooled, generating excess system noise. Worst-Case Peripheral Power Consumption The tendency is to design to data sheet maximums for peripheral components (again overcooling the system). Worst-Case Assembly Every system is unique because of manufacturing variations. Heat sinks may be loose fitting or slightly misaligned. Too much or too little thermal grease might be used, or variations in application pressure for thermal interface material could affect the efficiency of the thermal solution. Accounting for manufacturing variations in every system is difficult; therefore, the system must be designed for worst-case conditions.
TA HEAT SINK THERMAL INTERFACE MATERIAL INTEGRATED HEAT SPREADER SA TIMS CTIM TIMC PROCESSOR TTIM TJ
04498-073
*
*
*
TS TTIM TC CS
CA
*
JA
JTIM SUBSTRATE EPOXY THERMAL INTERFACE MATERIAL
Figure 51. Thermal Model
Although a design usually accounts for such worst-case conditions, the system is almost never operated at worst-case conditions. An alternative to designing for the worst case is to use the dynamic TMIN control function.
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ADT7467
Dynamic TMIN Control Overview
Dynamic TMIN control mode builds on the basic automatic fan control loop by adjusting the TMIN value based on system performance and measured temperature. Therefore, instead of designing for the worst case, the system thermals can be defined as operating zones. ADT7467 can self-adjust its fan control loop to maintain either an operating zone temperature or a system target temperature. For example, users can specify that the ambient temperature in a system be maintained at 50C. If the temperature is below 50C, the fans may not run or may run very slowly. If the temperature is higher than 50C, the fans may throttle up. The challenge presented by any thermal design is finding the right settings to suit the system's fan control solution. This can involve designing for the worst case, followed by weeks of system thermal characterization, and finally fan acoustic optimization (for psychoacoustic reasons). Optimizing the automatic fan control mode involves characterizing the system to determine the best TMIN and TRANGE settings for the control loop and the PWMMIN value that produces the quietest fan speed setting. Using the ADT7467 dynamic TMIN control mode, however, shortens the characterization time and alleviates tweaking the control loop settings because the device can selfadjust during system operation. Dynamic TMIN control mode is operated by specifying the operating zone temperatures required for the system. Associated with this control mode are three operating point registers, one for each temperature channel. This allows the system thermal solution to be broken down into distinct thermal zones. For example, CPU operating temperature is 70C, VRM operating temperature is 80C, and ambient operating temperature is 50C. The ADT7467 dynamically alters the control solution to maintain each zone temperature as closely as possible to its target operating point. Figure 52 shows an overview of the parameters that affect the operation of the dynamic TMIN control loop.
PWM DUTY CYCLE
TEMPERATURE TLOW TMIN OPERATING THIGH TTHERM TRANGE POINT
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Figure 52. Dynamic TMIN Control Loop
Table 14 provides a brief description of each parameter. Table 14. TMIN Control Loop Parameters
Parameter TLOW Description If the temperature drops below the TLOW limit, an error flag is set in a status register and an SMBALERT interrupt can be generated. If the temperature exceeds the THIGH limit, an error flag is set in a status register and an SMBALERT interrupt can be generated. The temperature at which the fan turns on in automatic fan speed control mode. The target temperature for a particular temperature zone. The ADT7467 attempts to maintain system temperature at approximately the operating point by adjusting the TMIN parameter of the control loop. If the temperature exceeds this critical limit, the fans can run at 100% for maximum cooling. Programs the PWM duty cycle vs. temperature control slope.
THIGH
TMIN Operating Point
TTHERM TRANGE
Dynamic TMIN Control Programming
Because the dynamic TMIN control mode is a basic extension of the automatic fan control mode, program the automatic fan control mode parameters as described in Step 1 to Step 8 in the Programming the Automatic Fan Speed Control Loop section, and then proceed with dynamic TMIN control mode programming.
Operating Point Registers
Register 0x33, Remote 1 operating point = 0xA4 (100C default) Register 0x34, local operating point = 0xA4 (100C default) Register 0x35, Remote 2 operating point = 0xA4 (100C default)
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ADT7467 PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP
To more efficiently understand the automatic fan speed control loop, it is strongly recommended to use the ADT7467 evaluation board and software while reading this section. This section provides the system designer with an understanding of the automatic fan control loop and provides step-by-step guidance on effectively evaluating and selecting critical system parameters. To optimize the system characteristics, the designer should consider several aspects of the system configuration, including the number of fans, where fans are located, and what temperatures are measured. The mechanical or thermal engineer who is tasked with the system thermal characterization should also be involved at the beginning of the process. * * * TACH4 fan speed measurement or overtemperature THERM function 5 V voltage monitoring or overtemperature THERM function 12 V voltage monitoring or VID5 input
2.
3.
STEP 1: HARDWARE CONFIGURATION
The motherboard sensing and control capabilities should be addressed in the early stages of designing a system, and decisions about how these capabilities are used should involve the system's thermal/mechanical engineer. Ask the following questions: 1. What ADT7467 functionality will be used? * PWM2 or SMBALERT 4.
The ADT7467 offers multifunctional pins that can be reconfigured to suit different system requirements and physical layouts. These multifunction pins are software programmable. How many fans will be supported in the system, three or four? This influences the choice of whether to use the TACH4 pin or to reconfigure it for the THERM function. Will the CPU fan be controlled using the ADT7467, or will it run at full speed 100% of the time? Running it at 100% frees up a PWM output, but the system is louder. Where will the ADT7467 be physically located in the system? This influences the assignment of the temperature measurement channels to particular system thermal zones. For example, locating the ADT7467 close to the VRM controller circuitry allows the VRM temperature to be monitored using the local temperature channel.
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 2 = CPU TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 53. Hardware Configuration Example
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04498-055
ADT7467
Recommended Implementation
Configuring the ADT7467 as shown in Figure 54 provides the system designer with the following features: * * * * Two PWM outputs for control of up to three fans. (The front and rear chassis fans are connected in parallel.) Three TACH fan speed measurement inputs. VCC measured internally through Pin 3. CPU core voltage measurement (VCORE). * * * CPU temperature measured using the Remote 1 temperature channel. Ambient temperature measured through the Remote 2 temperature channel. The bidirectional THERM pin allows monitoring PROCHOT output from, for example, an Intel Pentium 4 processor, or it can be used as an overtemperature THERM output. SMBALERT system interrupt output.
*
FRONT CHASSIS FAN
ADT7467
TACH2 PWM1 TACH1 CPU FAN
REAR CHASSIS FAN
PWM3 TACH3 D2+ D2- THERM PROCHOT
CPU
AMBIENT TEMPERATURE
D1+ D1- SDA SCL SMBALERT VCCP ICH
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GND
Figure 54. Recommended Implementation
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ADT7467
STEP 2: CONFIGURING THE MUX
After the system hardware configuration is determined, the fans can be assigned to particular temperature channels. Not only can fans be assigned to individual channels, but the behavior of the fans is also configurable. For example, fans can run using automatic fan control, can run manually (using software control), or can run at the fastest speed calculated by multiple temperature channels. The mux is the bridge between temperature measurement channels and the three PWM outputs. Bits <7:5> (BHVR) of Register 0x5C, Register 0x5D, and Register 0x5E (PWM configuration registers) control the behavior of the fans connected to the PWM1, PWM2, and PWM3 outputs. The values selected for these bits determine how the mux connects a temperature measurement channel to a PWM output. 010 = Remote 2 temperature controls PWMx 101 = fastest speed calculated by local and Remote 2 temperature controls PWMx 110 = fastest speed calculated by all three temperature channels controls PWMx The fastest speed calculated option pertains to controlling one PWM output based on multiple temperature channels. The thermal characteristics of the three temperature zones can be set to drive a single fan. An example would be the fan turning on when the Remote 1 temperature exceeds 60C or when the local temperature exceeds 45C.
Other Mux Options
<7:5> (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E 011 = PWMx runs at full speed 100 = PWMx disabled (default) 111 = manual mode. PWMx is run using software control. In this mode, PWM duty cycle registers (Register 0x30 to Register 0x32) are writable and control the PWM outputs.
MUX
Automatic Fan Control Mux Options
<7:5> (BHVR), Register 0x5C, Register 0x5D, and Register 0x5E 000 = Remote 1 temperature controls PWMx 001 = local temperature controls PWMx
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 2 = CPU TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 55. Assigning Temperature Channels to Fan Channels
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ADT7467
Mux Configuration Example
This is an example of how to configure the mux in a system using the ADT7467 to control three fans. The CPU fan sink is controlled by PWM1, the front chassis fan is controlled by PWM2, and the rear chassis fan is controlled by PWM3. The mux is configured for the following fan control behavior: * PWM1 (CPU fan sink) is controlled by the fastest speed calculated by the local (VRM temperature) and Remote 2 (processor) temperature. In this case, the CPU fan sink is also used to cool the VRM. PWM2 (front chassis fan) is controlled by the Remote 1 temperature (ambient). PWM3 (rear chassis fan) is controlled by the Remote 1 temperature (ambient).
Example Mux Settings
<7:5> (BHVR), PWM1 Configuration Register 0x5C 101 = fastest speed calculated by local and Remote 2 temperature controls PWM1 <7:5> (BHVR), PWM2 Configuration Register 0x5D 000 = Remote 1 temperature controls PWM2 <7:5> (BHVR), PWM3 Configuration Register 0x5E 000 = Remote 1 temperature controls PWM3 These settings configure the mux as shown in Figure 56.
* *
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0%
THERMAL CALIBRATION
MUX
100%
PWM MIN
TACHOMETER 1 MEASUREMENT
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TMIN TRANGE 0% PWM MIN TACHOMETER 2 MEASUREMENT
PWM2
LOCAL = VRM TEMP
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 56. Mux Configuration Example
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ADT7467
STEP 3: TMIN SETTINGS FOR THERMAL CALIBRATION CHANNELS
TMIN is the temperature at which the fans start to turn on when using automatic fan control mode. The speed at which the fan runs at TMIN is programmed later. The TMIN values chosen are temperature-channel specific, for example, 25C for ambient channel, 30C for VRM temperature, and 40C for processor temperature. TMIN is an 8-bit value, either twos complement or Offset 64, that can be programmed in 1C increments. There is a TMIN register associated with each temperature measurement channel: Remote 1, local, and Remote 2 temperature. Once the TMIN value is exceeded, the fan turns on and runs at the minimum PWM duty cycle. The fan turns off once the temperature has dropped below TMIN - THYST. To overcome fan inertia, the fan spins up until two valid TACH rising edges are counted. See the Fan Start-Up Timeout section for more details. In some cases, primarily for psychoacoustic reasons, it is desirable that the fan never switch off below TMIN. When set, Bits <7:5> of the Enhanced Acoustics Register 1 (0x62) keep the fans running at the PWM minimum duty cycle if the temperature falls below TMIN.
TMIN Registers
Register 0x67, Remote 1 temperature TMIN = 0x9A (90C) Register 0x68, local temperature TMIN = 0x9A (90C) Register 0x69, Remote 2 temperature TMIN = 0x9A (90C)
Enhanced Acoustics Register 1 (0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle when the temperature is below TMIN - THYST. Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle when the temperature is below TMIN - THYST. Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle when the temperature is below TMIN - THYST.
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ADT7467
100%
PWM DUTYCYCLE
0% TMIN
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 57. Understanding the TMIN Parameter
STEP 4: PWMMIN FOR PWM (FAN) OUTPUTS
PWMMIN is the minimum PWM duty cycle at which each fan in the system runs. It is also the start speed for each fan in automatic fan control mode when the temperature rises above TMIN. For maximum system acoustic benefit, PWMMIN should be as low as possible. Depending on the fan used, the PWMMIN setting is usually in the 20% to 33% duty cycle range. This value can be found through fan validation.
100% PWM DUTY CYCLE
More than one PWM output can be controlled from a single temperature measurement channel. For example, Remote 1 temperature can control PWM1 and PWM2 outputs. If two fans are used on PWM1 and PWM2, each fan's characteristics can be set up differently. As a result, Fan 1 driven by PWM1 can have a different PWMMIN value than that of Fan 2 connected to PWM2. In Figure 59, PWM1MIN (front fan) is turned on at a minimum duty cycle of 20%, and PWM2MIN (rear fan) turns on at a minimum of 40% duty cycle; however, both fans turn on at the same temperature, defined by TMIN.
100%
PWM DUTY CYCLE
PW
M2 M1
PWMMIN 0%
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PWM2MIN PWM1MIN 0%
PW
Figure 58. PWMMIN Determines Minimum PWM Duty Cycle
TMIN
TEMPERATURE
Figure 59. Operating Two Fans from a Single Temperature Channel
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TMIN
TEMPERATURE
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ADT7467
Programming the PWMMIN Registers
PWM DUTY CYCLE
The PWMMIN registers are 8-bit registers that allow the minimum PWM duty cycle for each output to be configured from 0% to 100%. This allows the minimum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMIN register is given by Value (decimal) = PWMMIN/0.39% Example 1: For a minimum PWM duty cycle of 50%, Value (decimal) = 50%/0.39% = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal) Example 2: For a minimum PWM duty cycle of 33%, Value (decimal) = 33%/0.39% = 85 (decimal) Value = 85 (decimal)l or 0x54 (hexadecimal)
100% PWMMAX
PWMMIN 0% TMIN TEMPERATURE
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Figure 60. PWMMAX Determines Maximum PWM Duty Cycle Below the THERM Temperature Limit
Programming the PWMMAX Registers
The PWMMAX registers are 8-bit registers that allow the maximum PWM duty cycle for each output to be configured from 0% to 100%. This allows the maximum PWM duty cycle to be set in steps of 0.39%. The value to be programmed into the PWMMAX register is given by Value (decimal) = PWMMAX/0.39% Example 1: For a maximum PWM duty cycle of 50%, Value (decimal) = 50%/0.39% = 128 (decimal) Value = 128 (decimal) or 0x80 (hexadecimal) Example 2: For a minimum PWM duty cycle of 75%, Value (decimal) = 75%/0.39% = 192 (decimal) Value = 192 (decimal) or 0xC0 (hexadecimal)
PWMMIN Registers
Register 0x64, PWM1 minimum duty cycle = 0x80 (50% default) Register 0x65 PWM2 minimum duty cycle = 0x80 (50% default) Register 0x66, PWM3 minimum duty cycle = 0x80 (50% default)
Fan Speed and PWM Duty Cycle
The PWM duty cycle does not directly correlate to fan speed in RPM. Running a fan at 33% PWM duty cycle does not equate to running the fan at 33% speed. Driving a fan at 33% PWM duty cycle runs the fan at closer to 50% of its full speed, because fan speed as a percentage of RPM generally relates to the square root of the PWM duty cycle. Given a PWM square wave as the drive signal, fan speed in RPM approximates to % fan speed = PWM duty cycle x 10
PWMMAX Registers
Register 0x38, PWM1 maximum duty cycle = 0xFF (100% default) Register 0x39, PWM2 maximum duty cycle = 0xFF (100% default) Register 0x3A, PWM3 maximum duty cycle = 0xFF (100% default) See the Fan Speed and PWM Duty Cycle section.
STEP 5: PWMMAX FOR PWM (FAN) OUTPUTS
PWMMAX is the maximum duty cycle that each fan in the system runs at during the automatic fan speed control loop. For maximum system acoustic benefit, PWMMAX should be as low as possible but capable of keeping the processor below its maximum temperature limit, even in a worst-case scenario. If the THERM temperature limit is exceeded, the fans are still boosted to 100% for fail-safe cooling. There is a PWMMAX limit for each fan channel. The default value of this register is 0xFF and, therefore, has no effect unless it is programmed.
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ADT7467
STEP 6: TRANGE FOR TEMPERATURE CHANNELS
TRANGE is the range of temperature over which automatic fan control occurs once the programmed TMIN temperature has been exceeded. TRANGE is a temperature slope, not an arbitrary value, that is, a TRANGE of 40C holds true only for PWMMIN = 33%. If PWMMIN is increased or decreased, the effective TRANGE changes.
TRANGE 100%
TRANGE is implemented as a slope, which means that as PWMMIN is changed, TRANGE changes, but the actual slope remains the same. The higher the PWMMIN value, the smaller the effective TRANGE, that is, the fan reaches full speed (100%) at a lower temperature.
100%
PWM DUTY CYCLE
50% 33% 25% 10% 0%
PWM DUTY CYCLE
PWMMIN 0%
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30C 40C 45C 54C TMIN
TMIN
TEMPERATURE
Figure 61. TRANGE Parameter Affects Cooling Slope
Figure 63. Increasing PWMMIN Changes Effective TRANGE
The TRANGE or fan control slope is determined by the following procedure: 1. 2. Determine the maximum operating temperature for that channel (for example, 70C). Through experimentation, determine the fan speed (PWM duty cycle value) that does not exceed the temperature at the worst-case operating points. (For example, 70C is reached when the fans are running at 50% PWM duty cycle.) Determine the slope of the required control loop to meet these requirements. The ADT7467 evaluation software can graphically program and visualize this functionality. Ask your local Analog Devices sales representative for details.
100%
PWM DUTY CYCLE
For a given TRANGE value, the temperature at which the fan runs at full speed, which varies with the PWMMIN value, can be easily calculated. TMAX = TMIN + (Max DC - Min DC) x TRANGE /170 where: TMAX is the temperature at which the fan runs full speed. TMIN is the temperature at which the fan turns on. Max DC is the maximum duty cycle (100%) = 255 decimal. Min DC is equal to PWMMIN. TRANGE is the duty PWM duty cycle vs. temperature slope. Example 1: Calculate T, given that TMIN = 30C, TRANGE = 40C, and PWMMIN = 10% duty cycle = 26 (decimal). TMAX = TMIN + (Max DC - Min DC) x TRANGE /170 TMAX = 30C + (100% - 10%) x 40C/170 TMAX = 30C + (255 - 26) x 40C/170 TMAX = 84C (Effective TRANGE = 54C) Example 2: Calculate TMAX, given that TMIN = 30C, TRANGE = 40C, and PWMMIN = 25% duty cycle = 64 (decimal).
3. 4.
50% 33% 0% 30C 40C TMIN
04498-065
TMAX = TMIN + (Max DC - Min DC) x TRANGE /170 TMAX = 30C + (100% - 25%) x 40C/170 TMAX = 30C + (255 - 64) x 40C/170 TMAX = 75C (Effective TRANGE = 45C) Example 3: Calculate TMAX, given that TMIN = 30C, TRANGE = 40C, and PWMMIN = 33% duty cycle = 85 (decimal). TMAX = TMIN + (Max DC - Min DC) x TRANGE /170 TMAX = 30C + (100% - 33%) x 40C/170 TMAX = 30C + (255 - 85) x 40C/170 TMAX = 70C (Effective TRANGE = 40C)
Figure 62. Adjusting PWMMIN Affects TRANGE
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ADT7467
Example 4: Calculate TMAX, given that TMIN = 30C, TRANGE = 40C, and PWMMIN = 50% duty cycle = 128 (decimal). TMAX = TMIN + (Max DC - Min DC) x TRANGE /170 TMAX = 30C + (100% - 50%) x 40C/170 TMAX = 30C + (255 - 128) x 40C/170 TMAX = 60C (Effective TRANGE = 30C) See the Fan Speed and PWM Duty Cycle section. Figure 64 shows PWM duty cycle vs. temperature for each TRANGE setting. The lower graph shows how each TRANGE setting affects fan speed vs. temperature. As can be seen from the graph, the effect on fan speed is nonlinear.
100 90 80
PWM DUTY CYCLE (%)
2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.3C 16C 20C 26.6C 32C 40C 53.3C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 80C
Selecting a TRANGE Slope
The TRANGE value can be selected for each temperature channel: Remote 1, local, and Remote 2 temperature. Bits <7:4> (TRANGE) of Register 0x5F to Register 0x61 define the TRANGE value for each temperature channel. Table 15. Selecting a TRANGE Value
Bits <7:4>1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
1
70 60 50 40 30 20 10 0 0
TRANGE (C) 2 2.5 3.33 4 5 6.67 8 10 13.33 16 20 26.67 32 (default) 40 53.33 80
100 90 80
FAN SPEED (% OF MAX)
2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.3C 16C 20C 26.6C 32C 40C 53.3C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120
04498-067
70 60 50 40 30 20 10 0 0
80C
Register 0x5F configures Remote 1 TRANGE. Register 0x60 configures local TRANGE. Register 0x61 configures Remote 2 TRANGE.
Figure 64. TRANGE vs. Fan Speed Profile
Summary of TRANGE Function
When using the automatic fan control function, the temperature at which the fan reaches full speed can be calculated by TMAX = TMIN + TRANGE Equation 1 holds true only when PWMMIN is equal to 33% PWM duty cycle. Increasing or decreasing PWMMIN changes the effective TRANGE, but the fan control still follows the same PWM duty cycle to temperature slope. The effective TRANGE for a PWMMIN value can be calculated using Equation 2: TMAX = TMIN + (Max DC - Min DC) x TRANGE/170 (2) (1)
The graphs in Figure 64 assume that the fan starts from 0% PWM duty cycle. The minimum PWM duty cycle, PWMMIN, must be factored in to determine how the loop performs in the system. Figure 65 shows how TRANGE is affected when the PWMMIN value is set to 20%. It can be seen that the fan runs at about 45% fan speed when the temperature exceeds TMIN.
where: (Max DC - Min DC) x TRANGE/170 is the effective TRANGE value.
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ADT7467
100 90 80
PWM DUTY CYCLE (%)
2C 2.5C 3.33C 4C PWM DUTY CYCLE (%) 5C 6.67C 8C 10C 13.3C 16C 20C 26.6C 32C 40C 53.3C 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120 80C
100 90 80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100
70 60 50 40 30 20 10 0 0
TEMPERATURE ABOVE TMIN
2C 2.5C 3.33C 4C 5C 6.67C 8C 10C 13.3C 16C 20C 26.6C 32C 40C 53.3C 80C FAN SPEED (% MAX RPM)
100 90 80
FAN SPEED (% OF MAX)
100 90 80 70 60 50 40 30 20 10
04498-068
70 60 50 40 30 20 10 0 0 20 40 60 80 TEMPERATURE ABOVE TMIN 100 120
TEMPERATURE ABOVE TMIN
Figure 65. TRANGE and Percentage of Fan Speed Slopes with PWMMIN = 20%
Figure 66. TRANGE and Percentage of Fan Speed Slopes for VRM, Ambient, and CPU Temperature Channels
Determining TRANGE for Each Temperature Channel
The following example shows how different TMIN and TRANGE settings can be applied to three thermal zones. In this example, the following TRANGE values apply: TRANGE = 80C for ambient temperature TRANGE = 53.3C for CPU temperature TRANGE = 40C for VRM temperature This example uses the mux configuration described in the Step 2: Configuring the Mux section, with the ADT7467 connected as shown in Figure 56. Both CPU temperature and VRM temperature drive the CPU fan connected to PWM1. Ambient temperature drives the front chassis fan and the rear chassis fan connected to PWM2 and PWM3. The front chassis fan is configured to run at PWMMIN = 20%; the rear chassis fan is configured to run at PWMMIN = 30%. The CPU fan is configured to run at PWMMIN = 10%.
STEP 7: TTHERM FOR TEMPERATURE CHANNELS
TTHERM is the absolute maximum temperature allowed on a temperature channel. Above this temperature, a component such as the CPU or VRM might be operating beyond its safe operating limit. When the temperature measured exceeds TTHERM, all fans are driven at 100% PWM duty cycle (full speed) to provide critical system cooling. The fans remain running at 100% until the temperature drops below TTHERM minus hysteresis, where hysteresis is the number programmed into the Hysteresis Registers 0x6D and 0x6E. The default hysteresis value is 4C. The TTHERM limit should be considered the maximum worst-case operating temperature of the system. Because exceeding any TTHERM limit runs all fans at 100%, it has significant negative acoustic effects. Ultimately, this limit should be set up as a failsafe, and users should ensure that it is not exceeded under normal system operating conditions.
4-Wire Fans
The control range for 4-wire fans is much wider than that of 2-wire or 3-wire fans. In many cases, 4-wire fans can start with a PWM drive of as little as 20%.
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0 0
10
20
30
40
50
60
70
80
90
100
ADT7467
Note that the TTHERM limits are nonmaskable and affect the fan speed regardless of the configuration of the automatic fan control settings. This allows some flexibility, because a TRANGE value can be selected based on its slope, and a hard limit (such as 70C) can be programmed as TMAX (the temperature at which the fan reaches full speed) by setting TTHERM to that limit (for example, 70C).
Hysteresis Registers
Register 0x6D, Remote 1 and local hysteresis register <7:4>, Remote 1 temperature hysteresis (4C default) <3:0>, local temperature hysteresis (4C default) Register 0x6E, Remote 2 temperature hysteresis register <7:4>, Remote 2 temperature hysteresis (4C default) Because each hysteresis setting is four bits, hysteresis values are programmable from 1C to 15C. It is recommended that hysteresis values are not programmed to 0C because this disables hysteresis. In effect, this would cause the fans to cycle between normal speed and 100% speed, creating unsettling acoustic noise.
THERM Limit Registers
Register 0x6A, Remote 1 THERM limit = 0xA4 (100C default) Register 0x6B, local THERM limit = 0xA4 (100C default) Register 0x6C, Remote 2 THERM limit = 0xA4 (100C default)
TRANGE 100%
PWM DUTYCYCLE
0% TMIN TTHERM
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 67. How TTHERM Relates to Automatic Fan Control
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ADT7467
STEP 8: THYST FOR TEMPERATURE CHANNELS
THYST is the amount of extra cooling a fan provides after the temperature measured drops below TMIN before the fan turns off. The premise for temperature hysteresis (THYST) is that, without it, the fan would merely chatter or cycle on and off repeatedly whenever the temperature hovered near the TMIN setting. The THYST value determines the amount of time needed for the system to cool down or heat up as the fan turns on and off. Values of hysteresis are programmable in the range 1C to 15C. Larger values of THYST prevent the fans from chattering on and off. The THYST default value is set at 4C. The THYST setting not only applies to the temperature hysteresis for fan on/off, but also is used for the TTHERM hysteresis value, as described in Step 6: TRANGE for Temperature Channels. Therefore, programming Register 0x6D and Register 0x6E sets the hysteresis for both fan on/off and the THERM function.
TRANGE 100%
PWM DUTYCYCLE
Hysteresis Registers
Register 0x6D, Remote 1 and local hysteresis register <7:4>, Remote 1 temperature hysteresis (4C default) <3:0>, local temperature hysteresis (4C default) Register 0x6E, Remote 2 temperature hysteresis register <7:4>, Remote 2 temperature hysteresis (4C default) In some applications, it is required that fans continue to run at PWMMIN, instead of turning off when the temperature drops below TMIN. Bits <7:5> of Enhanced Acoustics Register 1 (0x62) allow the fans to be either turned off or kept spinning below TMIN. If the fans are always on, the THYST value has no effect on the fan when the temperature drops below TMIN.
0% TMIN TTHERM
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 68. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis
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ADT7467
Enhanced Acoustics Register 1 (0x62)
Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle below TMIN - THYST. Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle below TMIN - THYST. Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when the temperature is below TMIN - THYST. Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle below TMIN - THYST.
and eliminating the need to design for the worst case. If a sensible operating point value is chosen, any TMIN value can be selected in the system characterization. If the TMIN value is too low, the fans run sooner than required and the temperature is below the operating point. In response, the ADT7467 increases TMIN to keep the fans off longer and to allow the temperature zone to approach the operating point. Likewise, too high a TMIN value causes the operating point to be exceeded, and, in turn, the ADT7467 reduces TMIN to turn the fans on sooner to cool the system.
Programming Operating Point Registers
There are three operating point registers, one for each temperature channel. These 8-bit registers allow the operating point temperatures to be programmed with 1C resolution.
STEP 9: OPERATING POINTS FOR TEMPERATURE CHANNELS
The operating point for each temperature channel is the optimal temperature for that thermal zone. The hotter each zone is allowed to be, the more quiet the system, because the fans are not required to run as fast. The ADT7467 increases or decreases fan speeds as necessary to maintain the operating point temperature, allowing for system-to-system variations
Operating Point Registers
Register 0x33, Remote 1 operating point = 0xA4 (100C default) Register 0x34, local temperature operating point = 0xA4 (100C default) Register 0x35, Remote 2 operating point = 0xA4 (100C default)
THERMAL CALIBRATION
100% OPERATING POINT
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 1 MEASUREMENT
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 69. Operating Point Value Dynamically Adjusts Automatic Fan Control Settings
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ADT7467
STEP 10: HIGH AND LOW LIMITS FOR TEMPERATURE CHANNELS
If the temperature falls below the temperature channel's low limit, TMIN increases. This reduces fan speed, allowing the system to heat up. An interrupt can be generated when the temperature drops below the low limit. If the temperature increases above the temperature channel's high limit, TMIN decreases. This increases fan speed to cool down the system. An interrupt can be generated when the temperature rises above the high limit. However, the loop operation is not as simple as described in these steps. A number of conditions govern the situations in which TMIN can increase or decrease.
Programming High and Low Limits There are six limit registers; a high limit and a low limit are associated with each temperature channel. These 8-bit registers allow the high and low limit temperatures to be programmed with 1C resolution. Temperature Limit Registers Register 0x4E, Remote 1 temperature low limit = 0x01 default Register 0x4F, Remote 1 temperature high limit = 0x7F default Register 0x50, local temperature low limit = 0x01 default Register 0x51, local temperature high limit = 0x7F default Register 0x52, Remote 2 temperature low limit = 0x01 default Register 0x53, Remote 2 temperature high limit = 0x7F default How Dynamic TMIN Control Works
The basic premise is as follows: 1. Set the target temperature for the temperature zone, for example, the Remote 1 thermal diode. This value is programmed to the Remote 1 operating temperature register. As the temperature in that zone (Remote 1 temperature) exceeds the operating point temperature, TMIN is reduced and the fan speed increases. As the temperature drops below the operating point temperature, TMIN is increased and the fan speed is reduced.
WAIT n MONITORING CYCLES CURRENT TEMPERATURE MEASUREMENT T1(n) OPERATING POINT TEMPERATURE OP1 PREVIOUS TEMPERATURE MEASUREMENT T1 (n - 1)
Short Cycle and Long Cycle The ADT7467 implements two loops: a short cycle and a long cycle. The short cycle takes place every n monitoring cycles. The long cycle takes place every 2n monitoring cycles. The value of n is programmable for each temperature channel. The bits are located at the following register locations: Remote 1 = CYR1 = Bits <2:0> of Dynamic TMIN Control Register 2 (Address 0x37) Local = CYL = Bits <5:3> of Dynamic TMIN Control Register 2 (Address 0x37) Remote 2 = CYR2 = Bits <7:6> of Dynamic TMIN Control Register 2 and Bit 0 of Dynamic TMIN Control Register 1 (0x36)
Table 16. Cycle Bit Assignments
Code 000 001 010 011 100 101 110 111 Short Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Long Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
2.
Care should be taken when choosing the cycle time. A long cycle time means that TMIN is updated less often. If a system has very fast temperature transients, the dynamic TMIN control loop lags. If a cycle time is chosen that is too fast, the full benefit of changing TMIN might not be realized and will need to change upon the next cycle; in effect, it is overshooting. Some calibration is necessary to identify the most suitable response time. Figure 70 shows the steps taken during the short cycle.
3.
IS T1(n) > (OP1 - HYS) YES
NO
DO NOTHING
IS T1(n) - T1(n - 1) 0.25C NO
YES
DO NOTHING (SYSTEM IS COOLING OFF FOR CONSTANT)
IS T1(n) - T1(n - 1) = 0.5 - 0.75C IS T1(n) - T1(n - 1) = 1.0 - 1.75C IS T1(n) - T1(n - 1) > 2.0C
DECREASE T MIN BY 1C DECREASE T MIN BY 2C DECREASE T MIN BY 4C
04498-077
Figure 70. Short Cycle Steps
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ADT7467
Figure 71 shows the steps taken during the long cycle.
WAIT 2n MONITORING CYCLES CURRENT TEMPERATURE MEASUREMENT T1(n) OPERATING POINT TEMPERATURE OP1
temperature has increased between this monitoring cycle and the last monitoring cycle. For example, if the temperature has increased by 1C, then TMIN is reduced by 2C. Decreasing TMIN has the effect of increasing the fan speed, thus providing more cooling to the system. If the temperature slowly increases only in the range (OP1 - Hyst), that is, the change in temperature is 0.25C per short monitoring cycle, TMIN does not decrease. This allows small changes in temperature in the desired operating zone without changing TMIN. The long cycle makes no change to TMIN in the temperature range (OP - Hyst), because the temperature has not exceeded the operating temperature. Once the temperature exceeds the operating temperature, TMIN reduces by 1C per long cycle as long as the temperature remains above the operating temperature. This takes place in addition to the decrease in TMIN that occurs during the short cycle. In Figure 73, because the temperature is increasing at a rate of 0.25C per short cycle, no reduction in TMIN takes place during the short cycle. Once the temperature falls below the operating temperature, TMIN remains fixed, even when the temperature starts to increase slowly, because the temperature only increases at a rate of 0.25C per cycle.
IS T1(n) > OP1
YES
DECREASE TMIN BY 1C
NO IS T1(n) < LOW TEMP LIMIT AND TMIN < HIGH TEMP LIMIT YES AND TMIN < OP1 AND T1(n) > TMIN NO
INCREASE TMIN BY 1C
Figure 71. Long Cycle Steps
The following examples illustrate circumstances that may cause TMIN to increase, decrease, or stay the same.
Normal Operation--No TMIN Adjustment
* If measured temperature never exceeds the programmed operating point minus the hysteresis temperature, TMIN is not adjusted, that is, it remains at its current setting. If measured temperature never drops below the low temperature limit, TMIN is not adjusted.
THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS
*
04498-078
DO NOT CHANGE
Increasing the TMIN Cycle
When the temperature drops below the low temperature limit, TMIN can increase during the long cycle. Increasing TMIN has the effect of running the fan more slowly and, therefore, more quietly. The long cycle diagram in Figure 71 shows the conditions necessary for TMIN to increase. TMIN can increase if * The measured temperature falls below the low temperature limit. This means that the user must choose the low limit carefully. It should not be so low that the temperature never falls below it, because TMIN would never increase and the fans would run faster than necessary. TMIN is below the high temperature limit. TMIN is never allowed to exceed the high temperature limit. As a result, the high limit should be chosen carefully because it determines the high limit of TMIN. TMIN is below the operating point temperature. TMIN should never be allowed to increase above the operating point temperature, because the fans would not switch on until the temperature rose above the operating point. The temperature is above TMIN. The dynamic TMIN control is turned off below TMIN.
ACTUAL TEMP LOW TEMP LIMIT TMIN
Figure 72. Temperature Between Operating Point and Low Temperature Limit
Because neither the operating point minus the hysteresis temperature nor the low temperature limit has been exceeded, the TMIN value is not adjusted and the fan runs at a speed determined by the fixed TMIN and TRANGE values, defined in the automatic fan speed control mode in the Enhancing System Acoustics section.
04498-079
*
*
Operating Point Exceeded--TMIN Reduced
When the measured temperature is below the operating point temperature minus the hysteresis, TMIN remains the same. Once the temperature exceeds the operating temperature minus the hysteresis (OP1 - Hyst), TMIN decreases during the short cycle (see Figure 70) at a rate determined by the programmed value of n. This rate also depends on the amount that the *
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ADT7467
THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS
ACTUAL TEMP
TMIN LOW TEMP LIMIT
NO CHANGE IN TMIN HERE DUE TO ANY CYCLE, BECAUSE T1(n) - T1 (n - 1) 0.25C AND T1(n) < OP = > TMIN STAYS THE SAME
Figure 73. Effect of Exceeding Operating Point Minus Hysteresis Temperature
Figure 74 shows how TMIN increases when the current temperature is above TMIN but below the low temperature limit, and how TMIN is below the high temperature limit and below the operating point. Once the temperature rises above the low temperature limit, TMIN remains fixed.
THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS
THERM LIMIT OPERATING POINT HYSTERESIS
LOW TEMP LIMIT HIGH TEMP LIMIT TMIN
ACTUAL TEMP
04498-080
DECREASE HERE DUE TO SHORT CYCLE ONLY T1(n) - T1 (n - 1) = 0.5C OR 0.75C = > TMIN DECREASES BY 1C EVERY SHORT CYCLE
DECREASE HERE DUE TO LONG CYCLE ONLY T1(n) - T1 (n - 1) 0.25C AND T1(n) > OP = > TMIN DECREASES BY 1C EVERY LONG CYCLE
TMIN PREVENTED FROM INCREASING
Figure 75. TMIN Adjustments Limited by the High Temperature Limit
LOW TEMP LIMIT TMIN
ACTUAL TEMP
04498-081
STEP 11: MONITORING THERM
Using the operating point limit ensures that the dynamic TMIN control mode operates in the best possible acoustic position and that the temperature never exceeds the maximum operating temperature. Using the operating point limit allows TMIN to be independent of system-level issues because of its self-corrective nature. In PC design, the operating point for the chassis is usually the worst-case internal chassis temperature. The optimal operating point for the processor is determined by monitoring the thermal monitor in the Intel Pentium 4 processor. To do this, the PROCHOT output of the Pentium 4 is connected to the THERM input of the ADT7467. The operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the PROCHOT output pulls the THERM input low on the ADT7467. This reveals the maximum temperature at which the Pentium 4 can run before clock modulation occurs.
Figure 74. Increasing TMIN for Quiet Operation
Preventing TMIN from Reaching Full Scale
TMIN is dynamically adjusted; therefore, it is undesirable for TMIN to reach full scale (127C), because the fan would never switch on. As a result, TMIN is allowed to vary only within a specified range. * * * The lowest possible value for TMIN is -127C (twos complement mode) or -64C (Offset 64 mode). TMIN cannot exceed the high temperature limit. If the temperature is below TMIN, the fan switches off or runs at minimum speed and dynamic TMIN control is disabled.
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04498-082
ADT7467
Enabling the THERM Trip Point as the Operating Point
Bits <4:2> of the dynamic TMIN control Register 1 (0x36) enable/disable THERM monitoring to program the operating point. <7> R2T = 1 enables the dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Enhancing System Acoustics section.
Dynamic TMIN Control Register 1 (0x36)
<2> PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores THERM assertions. The Remote 1 operating point register reflects its programmed value. <3> PHTL = 1 copies the local current temperature to the local temperature operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTL = 0 ignores THERM assertions. The local temperature operating point register reflects its programmed value. <4> PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTR2 = 0 ignores THERM assertions. The Remote 2 operating point register reflects its programmed value.
STEP 12: RAMP RATE FOR ACOUSTIC ENHANCEMENT
The optimal ramp rate for acoustic enhancement can be determined through system characterization after completing the thermal optimization. If possible, the effect of each ramp rate should be logged to determine the best setting for a given solution.
Enhanced Acoustics Register 1 (0x62)
<2:0> ACOU selects the ramp rate for PWM1. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots = 3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec
Enhanced Acoustics Register 2 (0x63)
<2:0> ACOU3 selects the ramp rate for PWM3. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots = 3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec <6:4> ACOU2 selects the ramp rate for PWM2. 000 = 1 time slot = 35 sec 001 = 2 time slots = 17.6 sec 010 = 3 time slots = 11.8 sec 011 = 5 time slots = 7 sec 100 = 8 time slots = 4.4 sec 101 = 12 time slots = 3 sec 110 = 24 time slots = 1.6 sec 111 = 48 time slots = 0.8 sec Another way to view the ramp rates is as the time it takes for the PWM output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. This can be tested by
Enabling Dynamic TMIN Control Mode
Bits <7:5> of the dynamic TMIN control Register 1 (0x36) enable/disable dynamic TMIN control on the temperature channels.
Dynamic TMIN Control Register 1 (0x36)
<5> R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control Overview section. <6> LT = 1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Enhancing System Acoustics section.
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ADT7467
putting the ADT7467 into manual mode and changing the PWM output from 0% to 100% PWM duty cycle. The PWM output takes 35 sec to reach 100% when a ramp rate of 1 time slot is selected. Figure 76 shows remote temperature plotted against PWM duty cycle for enhanced acoustics mode. The ramp rate is set to 48, which corresponds to the fastest ramp rate. Assume that a new temperature reading is available every 115 ms. With these settings, it takes approximately 0.76 sec to go from 33% duty cycle to 100% duty cycle (full speed). Even though the temperature increases very rapidly, the fan ramps up to full speed gradually.
140 120 100
RTEMP (C)
Figure 78 shows the PWM output response for a ramp rate of 2. With these conditions, the fan takes about 17.6 sec to reach full running speed.
140 120 100 RTEMP (C) 100 120
80
80 PWM DUTY CYCLE (%) 60 40 20 0 40 60
120 RTEMP (C)
20
0
TIME (s)
17.6
80
PWM DUTY CYCLE (%)
Figure 78. Enhanced Acoustics Mode with Ramp Rate = 2
80 60 60 PWM DUTY CYCLE (%) 40 20 0 40
20
Figure 79 shows how the control loop reacts to temperature with the slowest ramp rate. The ramp rate is set to 1; all other control parameters are the same as they are for Figure 76 through Figure 78. With the slowest ramp rate selected, it takes 35 sec for the fan to reach full speed.
120 140 RTEMP (C) 100 120 100 80
0
TIME (s)
Figure 77 shows how a ramp rate of 8 affects the control loop. The overall response of the fan is slower than it is with a ramp rate of 48. Because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. In this case, it takes approximately 4.4 sec for the fan to reach full speed.
120 RTEMP (C) 100 140 120 100 PWM DUTY CYCLE (%) 60 60 40 40 20 20 0
04498-087
80 60 PWM DUTY CYCLE (%) 40 60 40 20 0
20
0
TIME (s)
35
80
PWM DUTY CYCLE (%)
Figure 79. Enhanced Acoustics Mode with Ramp Rate = 1
RTEMP (C)
80
As Figure 76 to Figure 79 show, the rate at which the fan reacts to a temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. The higher the ramp rate, the faster the fan reaches the newly calculated fan speed.
0
0
TIME (s)
4.4
Figure 77. Enhanced Acoustics Mode with Ramp Rate = 8
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04498-089
0
PWM DUTY CYCLE (%)
Figure 76. Enhanced Acoustics Mode with Ramp Rate = 48
RTEMP (C)
04498-086
0 0.76
04498-088
100
0
PWM DUTY CYCLE (%)
RTEMP (C)
ADT7467
Figure 80 shows the behavior of the PWM output as temperature varies. As the temperature increases, the fan speed ramps up. Small drops in temperature do not affect the ramp-up function because the newly calculated fan speed is higher than the previous PWM value. Enhanced acoustics mode allows the PWM output to be made less sensitive to temperature variations. This is dependent on the ramp rate selected and programmed into the enhanced acoustics registers.
90 80 70 60 PWM DUTY CYCLE (%) 90 80 70 60 50 RTEMP (C) 40 30 20
04498-090
Enhanced Acoustics Register 1 (0x62)
<2:0> ACOU selects the ramp rate for PWM1. 000 = 140 sec 001 = 70.4 sec 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec
PWM DUTY CYCLE (%)
Enhanced Acoustics Register 2 (0x63)
<2:0> ACOU3 selects the ramp rate for PWM3. 000 = 140 sec 001 = 70.4 sec 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec <6:4> ACOU2 selects the ramp rate for PWM2. 000 = 140 sec 001 = 70.4 sec 010 = 47.2 sec 011 = 28 sec 100 = 17.6 sec 101 = 12 sec 110 = 6.4 sec 111 = 3.2 sec
RTEMP (C)
50 40 30 20 10 0 TIME (s)
10 0
Figure 80. Fan Reaction to Temperature Variation in Enhanced Acoustics Mode
Slower Ramp Rates
The ADT7467 can be programmed for much longer ramp times by slowing the ramp rates. Each ramp rate can be slowed by a factor of 4.
PWM1 Configuration Register (0x5C)
<3> SLOW, a setting of 1 slows the ramp rate for PWM1 by 4.
PWM2 Configuration Register (0x5D)
<3> SLOW, a setting of 1 slows the ramp rate for PWM2 by 4.
PWM3 Configuration Register (0x5E)
<3> SLOW, a setting of 1 slows the ramp rate for PWM3 by 4. The following sections list the ramp-up times when the SLOW bit is set for each PWM output.
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ADT7467 ENHANCING SYSTEM ACOUSTICS
Automatic fan speed control mode reacts instantaneously to changes in temperature, that is, the PWM duty cycle immediately responds to temperature change. Any impulses in temperature can cause an impulse in fan noise. For psychoacoustic reasons, the ADT7467 can prevent the PWM output from reacting instantaneously to temperature changes. Enhanced acoustic mode controls the maximum change in PWM duty cycle at a given time. The objective is to prevent the fan from repeatedly cycling up and down, annoying the user.
ACOUSTIC ENHANCEMENT MODE OVERVIEW
Figure 81 shows a top-level overview of the ADT7467 automatic fan control circuitry and where acoustic enhancement fits in. Acoustic enhancement is intended as a postdesign tweak made by a system or mechanical engineer evaluating the best settings for the system. Having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. The goal is to implement a system that is acoustically pleasing and does not cause user annoyance due to fan cycling. It is important to realize that although a system may pass an acoustic noise requirement specification (for example, 36 dB), it fails the consumer test if the fan is annoying.
ACOUSTIC ENHANCEMENT THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR
PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1 CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
REAR CHASSIS
Figure 81. Acoustic Enhancement Smoothes Fan Speed Variations in Automatic Fan Speed Control
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04498-083
ADT7467
Approaches to System Acoustic Enhancement
There are two different approaches to implementing system acoustic enhancement: temperature-centric and fan-centric. The ADT7467 uses the fan-centric approach. The temperature-centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, Remote 1 temperature). The temperature values used to calculate the PWM duty cycle values are smoothed, reducing fan speed variation. However, this approach causes an inherent delay in updating fan speed and causes the thermal characteristics of the system to change. It also causes the system fans to run longer than necessary, because the fan's reaction is merely delayed. The user has no control over noise from different fans driven by the same temperature source. Consider, for example, a system in which control of a CPU cooler fan (on PWM1) and a chassis fan (on PWM2) use Remote 1 temperature. Because the Remote 1 temperature is smoothed, both fans are updated at exactly the same rate. If the chassis fan is much louder than the CPU fan, there is no way to improve its acoustics without changing the thermal solution of the CPU cooling fan. The fan-centric approach to system acoustic enhancement controls the PWM duty cycle, driving the fan at a fixed rate (for example, 6%). Each time the PWM duty cycle is updated, it is incremented by a fixed 6%. As a result, the fan ramps smoothly to its newly calculated speed. If the temperature starts to drop, the PWM duty cycle immediately decreases by 6% at every update. Therefore, the fan ramps up or down smoothly without inherent system delay. Consider, for example, controlling the same CPU cooler fan (on PWM1) and chassis fan (on PWM2) using Remote 1 temperature. The TMIN and TRANGE settings have been defined in automatic fan speed control mode; that is, thermal characterization of the control loop has been optimized. Now the chassis fan is noisier than the CPU cooling fan. Using the fan-centric approach, PWM2 can be placed into acoustic enhancement mode independently of PWM1. The acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the CPU cooling fan, even though both fans are controlled by Remote 1 temperature.
Effect of Ramp Rate on Enhanced Acoustics Mode
The PWM signal driving the fan has a period, T, given by the PWM drive frequency, f, because T = 1/f. For a given PWM period, T, the PWM period is subdivided into 255 equal time slots. One time slot corresponds to the smallest possible increment in the PWM duty cycle. A PWM signal of 33% duty cycle is, therefore, high for 1/3 x 255 time slots and low for 2/3 x 255 time slots. Therefore, a 33% PWM duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots.
PWM_OUT 33% DUTY CYCLE
85 TIME SLOTS
170 TIME SLOTS
04498-084
04498-085
PWM OUTPUT (ONE PERIOD) = 255 TIME SLOTS
Figure 82. 33% PWM Duty Cycle, Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable from the values 1, 2, 3, 5, 8, 12, 24, and 48. The ramp rates are discrete time slots. For example, if the ramp rate is 8, eight time slots are added or subtracted to increase or decrease, respectively, the PWM high duty cycle. Figure 83 shows how the enhanced acoustics mode algorithm operates.
READ TEMPERATURE
CALCULATE NEW PWM DUTY CYCLE
IS NEW PWM VALUE > PREVIOUS VALUE? YES INCREMENT PREVIOUS PWM VALUE BY RAMP RATE
NO
DECREMENT PREVIOUS PWM VALUE BY RAMP RATE
Figure 83. Enhanced Acoustics Algorithm
Enabling Acoustic Enhancement for Each PWM Output
Enhanced Acoustics Register 1 (0x62) <3> = 1 enables acoustic enhancement on PWM1 output. Enhanced Acoustics Register 2 (0x63) <7> = 1 enables acoustic enhancement on PWM2 output. <3> = 1 enables acoustic enhancement on PWM3 output.
The enhanced acoustics mode algorithm calculates a new PWM duty cycle based on the temperature measured. If the new PWM duty cycle value is greater than the previous PWM value, the previous PWM duty cycle value is incremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhanced acoustics registers. If the new PWM duty cycle value is less than the previous PWM value, the previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. Each time the PWM duty cycle is incremented or decremented, its value is stored as the previous PWM duty cycle for the next comparison. A ramp rate of 1 corresponds to one time slot, which is 1/255 of the PWM period. In enhanced acoustics mode, incrementing or decrementing by 1 changes the PWM output by 1/255 x 100%.
Rev. 3 | Page 58 of 77 | www.onsemi.com
ADT7467 REGISTER MAP
Table 17. ADT7467 Registers
Address
0x21 0x22 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x46 0x47 0x48 0x49 0x4E 0x4F
R/W
R R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R R R/W R/W R/W R/W R/W R/W
Description
VCCP reading VCC reading Remote 1 temperature Local temperature Remote 2 temperature TACH1 low byte TACH1 high byte TACH2 low byte TACH2 high byte TACH3 low byte TACH3 high byte TACH4 low byte TACH4 high byte PWM1 current duty cycle PWM2 current duty cycle PWM3 current duty cycle Remote 1 operating point Local temperature operating point Remote 2 operating point Dynamic TMIN Control Reg. 1 Dynamic TMIN Control Reg. 2 Max PWM1 duty cycle Max PWM2 duty cycle Max PWM3 duty cycle Device ID register Company ID number Revision number Configuration Register 1 Interrupt Status Register 1 Interrupt Status Register 2 VCCP low limit VCCP high limit VCC low limit VCC high limit Remote 1 temperature low limit Remote 1 temperature
Bit 7
9 9 9 9 9 7 15 7 15 7 15 7 15 7 7 7 7 7 7 R2T CYR2 7 7 7 7 7 VER VCC OOL D2 7 7 7 7 7 7
Bit 6
8 8 8 8 8 6 14 6 14 6 14 6 14 6 6 6 6 6 6 LT CYR2 6 6 6 6 6 VER TODIS R2T D1 6 6 6 6 6 6
Bit 5
7 7 7 7 7 5 13 5 13 5 13 5 13 5 5 5 5 5 5 R1T CYL 5 5 5 5 5 VER FSPDIS LT F4P 5 5 5 5 5 5
Bit 4
6 6 6 6 6 4 12 4 12 4 12 4 12 4 4 4 4 4 4 PHTR2 CYL 4 4 4 4 4 VER VxI R1T FAN3 4 4 4 4 4 4
Bit 3
5 5 5 5 5 3 11 3 11 3 11 3 11 3 3 3 3 3 3 PHTL CYL 3 3 3 3 3 STP FSPD RES FAN2 3 3 3 3 3 3
Bit 2
4 4 4 4 4 2 10 2 10 2 10 2 10 2 2 2 2 2 2 PHTR1 CYR1 2 2 2 2 2 STP RDY VCC FAN1 2 2 2 2 2 2
Bit 1
3 3 3 3 3 1 9 1 9 1 9 1 9 1 1 1 1 1 1 VCCPLO CYR1 1 1 1 1 1 STP LOCK VCCP OVT 1 1 1 1 1 1
Bit 0
2 2 2 2 2 0 8 0 8 0 8 0 8 0 0 0 0 0 0 CYR2 CYR1 0 0 0 0 0 STP STRT RES RES 0 0 0 0 0 0
Default
0x00 0x00 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xA4 0xA4 0xA4 0x00 0x00 0xFF 0xFF 0xFF 0x68 0x41 0x71/ 0x72 0x01 0x00 0x00 0x00 0xFF 0x00 0xFF 0x01 0x7F
Lockable
Yes Yes Yes Yes Yes
Yes
Rev. 3 | Page 59 of 77 | www.onsemi.com
ADT7467
Address
0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description
high limit Local temperature low limit Local temperature high limit Remote 2 temperature low limit Remote 2 temperature high limit TACH1 minimum low byte TACH1 minimum high byte TACH2 minimum low byte TACH2 minimum high byte TACH3 minimum low byte TACH3 minimum high byte TACH4 minimum low byte TACH4 minimum high byte PWM1 configuration register PWM2 configuration register PWM3 configuration register Remote 1 TRANGE/PWM1 frequency Local TRANGE/PWM2 frequency Remote 2 TRANGE/PWM3 frequency Enhanced acoustics Register 1 Enhanced acoustics Register 2 PWM1 min duty cycle PWM2 min duty cycle PWM3 min duty cycle Remote 1 temp TMIN Local temp TMIN Remote 2 temp TMIN Remote 1 THERM temperature limit Local THERM temperature limit Remote 2 THERM temperature limit Remote 1 and local
Bit 7
7 7 7 7 7 15 7 15 7 15 7 15 BHVR BHVR BHVR RANGE RANGE RANGE MIN3 EN2 7 7 7 7 7 7 7 7 7 HYSR1
Bit 6
6 6 6 6 6 14 6 14 6 14 6 14 BHVR BHVR BHVR RANGE RANGE RANGE MIN2 ACOU2 6 6 6 6 6 6 6 6 6 HYSR1
Bit 5
5 5 5 5 5 13 5 13 5 13 5 13 BHVR BHVR BHVR RANGE RANGE RANGE MIN1 ACOU2 5 5 5 5 5 5 5 5 5 HYSR1
Bit 4
4 4 4 4 4 12 4 12 4 12 4 12 INV INV INV RANGE RANGE RANGE SYNC ACOU2 4 4 4 4 4 4 4 4 4 HYSR1
Bit 3
3 3 3 3 3 11 3 11 3 11 3 11 SLOW SLOW SLOW THRM THRM THRM EN1 EN3 3 3 3 3 3 3 3 3 3 HYSL
Bit 2
2 2 2 2 2 10 2 10 2 10 2 10 SPIN SPIN SPIN FREQ FREQ FREQ ACOU ACOU3 2 2 2 2 2 2 2 2 2 HYSL
Bit 1
1 1 1 1 1 9 1 9 1 9 1 9 SPIN SPIN SPIN FREQ FREQ FREQ ACOU ACOU3 1 1 1 1 1 1 1 1 1 HYSL
Bit 0
0 0 0 0 0 8 0 8 0 8 0 8 SPIN SPIN SPIN FREQ FREQ FREQ ACOU ACOU3 0 0 0 0 0 0 0 0 0 HYSL
Default
0x01 0x7F 0x01 0x7F 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x82 0x82 0x82 0xC4 0xC4 0xC4 0x00 0x00 0x80 0x80 0x80 0x9A 0x9A 0x9A 0xA4 0xA4 0xA4 0x44
Lockable
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Rev. 3 | Page 60 of 77 | www.onsemi.com
ADT7467
Address
0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R R
Description
temp/TMIN hysteresis Remote 2 temp/TMIN hysteresis XNOR tree test enable Remote 1 temperature offset Local temperature offset Remote 2 temperature offset Configuration Register 2 Interrupt Mask 1 register Interrupt Mask 2 register Extended Resolution 1 Extended Resolution 2 Configuration Register 3 THERM timer status register THERM timer limit register TACH pulses per revolution Configuration Register 5 Configuration Register 4 Manufacturer's Test Register 1 Manufacturer's Test Register 2
Bit 7
HYSR2 RES 7 7 7 SHDN OOL D2 RES TDM2 DC4 TMR LIMT FAN4 RES RES
Bit 6
HYSR2 RES 6 6 6 CONV R2T D1 RES TDM2 DC3 TMR LIMT FAN4 RES RES
Bit 5
HYSR2 RES 5 5 5 ATTN LT F4P VCC LTMP DC2 TMR LIMT FAN3 RES
Bit 4
HYRS RES 4 4 4 AVG RIT FAN3 VCC LTMP DC1 TMR LIMT FAN3 RES
Bit 3
RES RES 3 3 3 AIN4 RES FAN2 VCCP TDM1 FAST TMR LIMT FAN2 GPIOP
Bit 2
RES RES 2 2 2 AIN3 VCC FAN1 VCCP TDM1 BOOST TMR LIMT FAN2 GPIOD
Bit 1
RES RES 1 1 1 AIN2 VCCP OVT RES RES THERM TMR LIMT FAN1 LF/HF Pin 9 Func
Bit 0
RES XEN 0 0 0 AIN1 RES RES RES RES ALERT Enable ASRT/TMR0 LIMT FAN1 Twos Compl Pin 9 Func
Default
0x40 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x55 0x00 0x00 0x00 0x00
Lockable
Yes Yes Yes Yes Yes Yes
Yes
Yes Yes Yes Yes
RES AINL AINL BpAtt VCCP Do not write to these registers Do not write to these registers
Table 18. Voltage Reading Registers (Power-On Default = 0x00)1 Register Address 0x21 0x22
1
R/W Read only Read only
Description Reflects the voltage measurement2 at the VCCP input on Pin 14 (8 MSBs of reading). Reflects the voltage measurement3 at the VCC input on Pin 3 (8 MSBs of reading).
If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 2 If VCCPLO (Bit 1 of the Dynamic TMIN Control Register 1, 0x36) is set, VCCP can control the sleep state of the ADT7467. 3 VCC (Pin 3) is the supply voltage for the ADT7467.
Table 19. Temperature Reading Registers (Power-On Default = 0x01)1, 2 Register Address 0x25 0x26 0x27
1 2
R/W Read only Read only Read only
Description Remote 1 temperature reading3, 4 (8 MSBs of reading). Local temperature reading (8 MSBs of reading). Remote 2 temperature reading (8 MSBs of reading).
These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C). If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen. 3 In twos complement mode, a temperature reading of -128C (0x80) indicates a diode fault (open or short) on that channel. 4 In Offset 64 mode, a temperature reading of -64C (0x00) indicates a diode fault (open or short) on that channel.
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ADT7467
Table 20. Fan Tachometer Reading Registers (Power-On Default = 0x00)1
Register Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F
1
R/W Read only Read only Read only Read only Read only Read only Read only Read only
Description TACH1 low byte. TACH1 high byte. TACH2 low byte. TACH2 high byte. TACH3 low byte. TACH3 high byte. TACH4 low byte. TACH4 high byte.
These registers count the number of 11.11 s periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2). The number of TACH pulses used to count can be changed using the TACH pulses per revolution register (0x7B). This allows the fan speed to be accurately measured. Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At power-on, these registers contain 0x0000 until the first valid fan TACH measurement is read into these registers. This prevents false interrupts from occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following: * Stalled or blocked (object jamming the fan). * Failed (internal circuitry destroyed). * Not populated. (The ADT7467 expects to see a fan connected to each TACH. If a fan is not connected to a TACH, the minimum high and low bytes of that TACH should be set to 0xFFFF.) * Alternate function (for example, TACH4 reconfigured as THERM pin). * 2-wire instead of 3-wire fan.
Table 21. Current PWM Duty Cycle Registers (Power-On Default = 0x00)1 Register Address 0x30 0x31 0x32
1
R/W Read/write Read/write Read/write
Description PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF). PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).
These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7467 reports the PWM duty cycles through these registers. The PWM duty cycle values vary according to the temperature in automatic fan speed control mode. During fan startup, these registers report 0x00. In software mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.
Table 22. Operating Point Registers (Power-On Default = 0xA4)1, 2, 3 Register Address 0x33 0x34 0x35
1 2
R/W Read/write Read/write Read/write
Description Remote 1 operating point register (default = 100C). Local temperature operating point register (default = 100C). Remote 2 operating point register (default = 100C).
These registers set the target operating point for each temperature channel when the dynamic TMIN control feature is enabled. The fans being controlled are adjusted to maintain temperature about an operating point. 3 These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7467
Table 23. Register 0x36--Dynamic TMIN Control Register 1 (Power-On Default = 0x00)1 Bit <0> Name CYR2 R/W Read/write Description MSB of 3-bit Remote 2 cycle value. The other two bits of the code reside in Dynamic TMIN Control Register 2 (0x37). These three bits define the delay time, in terms of the number of monitoring cycles, for making subsequent TMIN adjustments in the control loop. The system is associated with thermal time constants that must be found to optimize the response of the fans and the control loop. VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below its VCCP low limit value (Register 0x46), the following occurs: Status Bit 1 in Interrupt Status Register 1 is set. SMBALERT is generated if enabled. PROCHOT monitoring is disabled. Dynamic TMIN control is disabled. The device is prevented from entering shutdown. Everything is re-enabled once VCCP increases above the VCCPLO limit. PHTR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to run as quietly as possible without affecting system performance. PHTR1 = 0 ignores THERM assertions on the THERM pin. The Remote 1 operating point register reflects its programmed value. PHTL = 1 copies the local channel's current temperature to the local operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted. This allows the system to run as quietly as possible without affecting system performance. PHTL = 0 ignores THERM assertions on the THERM pin. The local temperature operating point register reflects its programmed value. PHTR2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM is asserted. The operating point contains the temperature at which THERM is asserted, allowing the system to run as quietly as possible without affecting system performance. PHTR2 = 0 ignores THERM assertions on the THERM pin. The Remote 2 operating point register reflects its programmed value. R1T = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for the zone. R1T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section. LT = 1 enables dynamic TMIN control on the local temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for the zone. LT = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section. R2T = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for the zone. R2T = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Fan Speed Control section.
<1>
VCCPLO
Read/write
<2>
PHTR1
Read/write
<3>
PHTL
Read/write
<4>
PHTR2
Read/write
<5>
R1T
Read/write
<6>
LT
Read/write
<7>
R2T
Read/write
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7467
Table 24. Register 0x37--Dynamic TMIN Control Register 2 (Power-On Default = 0x00)1 Bit <2:0> Name CYR1 R/W Read/write Description 3-bit Remote 1 cycle value. These three bits define the delay time, in terms of the number of monitoring cycles, for making subsequent TMIN adjustments in the control loop for the Remote 1 channel. The system is associated with thermal time constants that must be found to optimize the response of the fans and the control loop. Bits Decrease (Short) Cycle Increase (Long) Cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) 3-bit local temperature cycle value. These three bits define the delay time, in terms of number of monitoring cycles, for making subsequent TMIN adjustments in the control loop for the local temperature channel. The system is associated with thermal time constants that must be found to optimize the response of the fans and the control loop. Bits Decrease (Short) Cycle Increase (Long) Cycle 000 8 cycles (1 sec) 16 cycles (2 sec) 001 16 cycles (2 sec) 32 cycles (4 sec) 010 32 cycles (4 sec) 64 cycles (8 sec) 011 64 cycles (8 sec) 128 cycles (16 sec) 100 128 cycles (16 sec) 256 cycles (32 sec) 101 256 cycles (32 sec) 512 cycles (64 sec) 110 512 cycles (64 sec) 1024 cycles (128 sec) 111 1024 cycles (128 sec) 2048 cycles (256 sec) 2 LSBs of 3-bit Remote 2 cycle value. The MSB of the 3-bit code resides in dynamic TMIN Control Register 1 (0x36). These three bits define the delay time, in terms of number of monitoring cycles, for making subsequent TMIN adjustments in the control loop for the Remote 2 channel. The system is associated with thermal time constants that must be found to optimize the response of fans and the control loop. Bits 000 001 010 011 100 101 110 111
1
<5:3>
CYL
Read/write
<7:6>
CYR2
Read/write
Decrease Cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec)
Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 25. Maximum PWM Duty Cycle Registers (Power-On Default = 0xFF)1 Register Address 0x38 0x39 0x3A
1
R/W Read/write Read/write Read/write
Description Maximum duty cycle for PWM1 output, default = 100% (0xFF). Maximum duty cycle for PWM2 output, default = 100% (0xFF). Maximum duty cycle for PWM3 output, default = 100% (0xFF).
These registers set the maximum PWM duty cycle of the PWM output.
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ADT7467
Table 26. Register 0x40--Configuration Register 1 (Power-On Default = 0x01)1 Bit <0> Name STRT R/W Read/write Description Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed. Logic 0 disables monitoring and PWM control based on the default power-up limit settings. Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the default settings are enabled. This bit becomes a read-only bit and cannot be changed once Bit 1 (LOCK bit) has been written. All limit registers should be programmed by BIOS before setting this bit to 1. (Lockable) Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become readonly registers and cannot be modified until the ADT7467 is powered down and powered up again. This prevents rogue programs such as viruses from modifying critical system limit settings. (Lockable) This bit is only set to 1 by the ADT7467 to indicate that the device is fully powered up and ready to begin system monitoring. When set to 1, this bit runs all fans at full speed. Power-on default = 0. This bit cannot be locked at any time. BIOS should set this bit to a 1 when the ADT7467 is configured to measure current from an ADI ADOPTTM VRM controller and to measure the CPU's core voltage. This bit allows monitoring software to display the watts used by the CPU. (Lockable) Logic 1 disables fan spin-up for two TACH pulses, and the PWM outputs go high for the entire fan spin-up timeout selected. When this bit is set to 1, the SMBus timeout feature is disabled. This allows the ADT7467 to be used with SMBus controllers that cannot handle SMBus timeouts. (Lockable) When this bit is set to 1, the ADT7467 rescales its VCC pin to measure 5 V supply. If this bit is 0, the ADT7467 measures VCC as a 3.3 V supply. (Lockable)
<1>
LOCK
Write once
<2> <3> <4>
RDY FSPD VxI
Read only Read/write Read/write
<5> <6> <7>
FSPDIS TODIS VCC
Read/write Read/write Read/write
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 27. Register 0x41--Interrupt Status Register 1 (Power-On Default = 0x00) Bit <1> <2> <4> <5> <6> <7> Name VCCP VCC R1T LT R2T OOL R/W Read only Read only Read only Read only Read only Read only Description VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared upon a read of the status register if the error condition has subsided. VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared upon a read of the status register if the error condition has subsided. R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared upon a read of the status register if the error condition has subsided. LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared upon a read of the status register if the error condition has subsided. R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared upon a read of the status register if the error condition has subsided. OOL = 1 indicates that an out-of-limit event has been latched in Status Register 2. This bit is a logical OR of all status bits in Status Register 2. Software can test this bit in isolation to determine whether any of the voltage, temperature, or fan speed readings represented by Status Register 2 are out of limit, which eliminates the need to read Status Register 2 at every interrupt or in every polling cycle.
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ADT7467
Table 28. Register 0x42--Interrupt Status Register 2 (Power-On Default = 0x00) Bit
<1> <2> <3> <4> <5>
Name
OVT FAN1 FAN2 FAN3 F4P
R/W
Read only Read only Read only Read only Read only Read/write Read only
Description
OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared upon a read of the status register when the temperature drops below THERM - THYST. FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when the PWM1 output is off. FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when the PWM2 output is off. FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. F4P = 1 indicates that Fan 4 has dropped below minimum speed or has stalled. This bit is not set when the PWM3 output is off. When Pin 9 is programmed as a GPIO output, writing to this bit determines the logic output of the GPIO. If Pin 9 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM assertion time exceeds the limit programmed in the THERM limit register (0x7A). D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs. D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.
<6> <7>
D1 D2
Read only Read only
Table 29. Voltage Limit Registers1 Register Address
0x46 0x47 0x48 0x49
1 2
R/W
Read/write Read/write Read/write Read/write
Description2
VCCP low limit. VCCP high limit. VCC low limit. VCC high limit.
Power-On Default
0x00 0xFF 0x00 0xFF
Setting the Configuration Register 1 LOCK bit has no effect on these registers. High limit: An interrupt is generated when a value exceeds its high limit (>comparison). Low limit: An interrupt is generated when a value is equal to or below its low limit (comparison).
Table 30. Temperature Limit Registers1 Register Address
0x4E 0x4F 0x50 0x51 0x52 0x53
1
R/W
Read/write Read/write Read/write Read/write Read/write Read/write
Description2
Remote 1 temperature low limit. Remote 1 temperature high limit. Local temperature low limit. Local temperature high limit. Remote 2 temperature low limit. Remote 2 temperature high limit.
Power-On Default
0x01 0x7F 0x01 0x7F 0x01 0x7F
Exceeding any temperature limit by 1C sets the appropriate status bit in the interrupt status register. Setting the Configuration Register 1 LOCK bit has no effect on these registers. 2 High limit: An interrupt is generated when a value exceeds its high limit (>comparison). Low limit: An interrupt is generated when a value is equal to or below its low limit (comparison).
Table 31. Fan Tachometer Limit Registers1 Register Address
0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B
1
R/W
Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write
Description
TACH1 minimum low byte. TACH1 minimum high byte/single-channel ADC channel select. TACH2 minimum low byte. TACH2 minimum high byte. TACH3 minimum low byte. TACH3 minimum high byte. TACH4 minimum low byte. TACH4 minimum high byte.
Power-On Default
0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
Exceeding any TACH limit register by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2 to indicate the fan failure. Setting the Configuration Register 1 LOCK bit has no effect on these registers.
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ADT7467
Table 32. Register 0x55--TACH 1 Minimum High Byte (Power-On Default = 0xFF)
Bit <4:0> <7:5> Name Reserved SCADC R/W Read only Read/write Description These bits are reserved when Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode). Otherwise, these bits represent Bits <4:0> of the TACH1 minimum high byte. When Bit 6 of Configuration 2 Register (0x73) is set (single-channel ADC mode), these bits are used to select the only channel from which the ADC makes measurements. Otherwise, these bits represent Bits <7:5> of the TACH1 minimum high byte.
Table 33. PWM Configuration Registers Register Address 0x5C 0x5D 0x5E
1
R/W1 Read/write Read/write Read/write
Description PWM1 configuration. PWM2 configuration. PWM3 configuration.
Power-On Default 0x82 0x82 0x82
These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 34. Register 0x5C, Register 0x5D, and Register 0x5E--PWM1, PWM2, and PWM3 Configuration Registers
(Power-On Default = 0x82)
Bit <2:0> Name SPIN R/W1 Read/write Description These bits control the start-up timeout for PWMx. The PWM output stays high until two valid TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH measurement immediately after the fan start-up timeout period, the TACH measurement reads 0xFFFF and Status Register 2 reflects the fan fault. If the TACH minimum high and low bytes contain 0xFFFF or 0x0000, the Status Register 2 bit is not set, even if the fan has not started. 000 = No start-up timeout 001 = 100 ms 010 = 250 ms (default) 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 4 sec SLOW = 1 makes the ramp rates for acoustic enhancement four times longer. This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for 100% duty cycle. Setting this bit to 1 inverts the PWM output so that 100% duty cycle corresponds to a logic low output. These bits assign each fan to a particular temperature sensor for localized cooling. 000 = Remote 1 temperature controls PWMx (automatic fan control mode). 001 = local temperature controls PWMx (automatic fan control mode). 010 = Remote 2 temperature controls PWMx (automatic fan control mode). 011 = PWMx runs at full speed. 100 = PWMx disabled (default). 101 = fastest speed calculated by local and Remote 2 temperature controls PWMx. 110 = fastest speed calculated by all three temperature channel controls PWMx. 111 = manual mode. PWM duty cycle registers (0x30 to 0x32) become writable.
<3> <4>
SLOW INV
Read/write Read/write
<7:5>
BHVR
Read/write
1
These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7467
Table 35. TRANGE/PWM Frequency Registers Register Address 0x5F 0x60 0x61
1
R/W1 Read/write Read/write Read/write
Description Remote 1 TRANGE/PWM1 frequency. Local TRANGE/PWM2 frequency. Remote 2 TRANGE/PWM3 frequency.
Power-On Default 0xC4 0xC4 0xC4
These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 36. Register 0x5F, Register 0x60, and Register 0x61--Remote 1, Local, and Remote 2 TRANGE/PWMx Frequency Registers
(Power-On Default = 0xC4)
Bit <2:0> Name FREQ R/W1 Read/write Description These bits control the PWMx frequency. 000 = 11.0 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz THRM = 1 causes the THERM pin (Pin 9) to assert low as an output when this temperature channel's THERM limit is exceeded by 0.25C. The THERM pin remains asserted until the temperature is equal to or below the THERM limit. The minimum time that THERM asserts is one monitoring cycle. This allows clock modulation of devices that incorporate this feature. THRM = 0 makes the THERM pin act as an input when Pin 9 is configured as THERM, for example, for Pentium 4 PROCHOT monitoring. These bits determine the PWM duty cycle vs. the temperature slope for automatic fan control. 0000 = 2C 0001 = 2.5C 0010 = 3.33C 0011 = 4C 0100 = 5C 0101 = 6.67C 0110 = 8C 0111 = 10C 1000 = 13.33C 1001 = 16C 1010 = 20C 1011 = 26.67C 1100 = 32C (default) 1101 = 40C 1110 = 53.33C 1111 = 80C
<3>
THRM
Read/write
<7:4>
RANGE
Read/write
1
These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7467
Table 37. Register 0x62--Enhanced Acoustics Register 1 (Power-On Default = 0x00) Bit <2:0> Name ACOU R/W1 Read/write Description These bits select the ramp rate applied to the PWM1 output. Instead of PWM1 jumping instantaneously to its newly calculated speed, PWM1 ramps gracefully at the rate determined by these bits. This feature enhances the acoustics of the fan being driven by the PWM1 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, acoustic enhancement is enabled on PWM1 output. SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to three fans to be driven from PWM3 output and their speeds to be measured. SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output. When the ADT7467 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN - hysteresis value. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM1 minimum duty cycle below TMIN - hysteresis. When the ADT7467 is in automatic fan speed control mode and the controlling temperature is below its TMIN - hysteresis value, this bit defines whether PWM2 is off (0% duty cycle) or at PWM2 minimum duty cycle. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM2 minimum duty cycle below TMIN - hysteresis. When the ADT7467 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN - hysteresis value. 0 = 0% duty cycle below TMIN - hysteresis. 1 = PWM3 minimum duty cycle below TMIN - hysteresis.
<3> <4>
EN1 SYNC
Read/write Read/write
<5>
MIN1
Read/write
<6>
MIN2
Read/write
<7>
MIN3
Read/write
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
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ADT7467
Table 38. Register 0x63--Enhanced Acoustics Register 2 (Power-On Default = 0x00) Bit <2:0> Name ACOU3 R/W1 Read/write Description These bits select the ramp rate applied to the PWM3 output. Instead of PWM3 jumping instantaneously to its newly calculated speed, PWM3 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fan being driven by the PWM3 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, acoustic enhancement is enabled on PWM3 output. These bits select the ramp rate applied to the PWM2 output. Instead of PWM2 jumping instantaneously to its newly calculated speed, PWM2 ramps gracefully at the rate determined by these bits. This effect enhances the acoustics of the fans being driven by the PWM2 output. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec When this bit is 1, acoustic enhancement is enabled on PWM2 output.
<3> <6:4>
EN3 ACOU2
Read/write Read/write
<7>
1
EN2
Read/write
This register becomes a read-only register when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 39. PWM Minimum Duty Cycle Registers Register Address 0x64 0x65 0x66
1
R/W1 Read/write Read/write Read/write
Description PWM1 minimum duty cycle. PWM2 minimum duty cycle. PWM3 minimum duty cycle.
Power-On Default 0x80 (50% duty cycle) 0x80 (50% duty cycle) 0x80 (50% duty cycle)
These registers become read-only registers when the ADT7467 is in automatic fan control mode.
Table 40. Register 0x64, Register 0x65, and Register 0x66--PWM1, PWM2, and PWM3 Minimum Duty Cycle Registers Bit <7:0> R/W1 Read/write Description These bits define the PWMMIN duty cycle for PWMx. 0x00 = 0% duty cycle (fan off ). 0x40 = 25% duty cycle. 0x80 = 50% duty cycle. 0xFF = 100% duty cycle (fan full speed).
1
These registers becomes a read-only register when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
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ADT7467
Table 41. TMIN Registers1 Register Address
0x67 0x68 0x69
1
R/W2
Read/write Read/write Read/write
Description
Remote 1 TMIN. Local TMIN. Remote 2 TMIN.
Power-On Default
0x9A (90C) 0x9A (90C) 0x9A (90C)
These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases with temperature according to TRANGE. 2 These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 42. THERM Temperature Limit Registers1 Register Address
0x6A 0x6B 0x6C
1
R/W2
Read/write Read/write Read/write
Description
Remote 1 THERM temperature limit. Local THERM temperature limit. Remote 2 THERM temperature limit.
Power-On Default
0xA4 (100C) 0xA4 (100C) 0xA4 (100C)
If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is disabled. The PWM output remains at 100% until the temperature drops below THERM limit - hysteresis. If the THERM pin is programmed as an output, exceeding these limits by 0.25C can cause the THERM pin to assert low as an output. 2 These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 43. Temperature/TMIN Hysteresis Registers1 Register Address
0x6D 0x6E
1
R/W2
Read/write Read/write
Description
Remote 1 and local temperature hysteresis. Remote 2 temperature hysteresis.
Power-On Default
0x44 0x40
Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN - hysteresis. Up to 15C of hysteresis can be assigned to any temperature channel. The hysteresis value chosen also applies to that temperature channel if its THERM limit is exceeded. If the THERM limit is exceeded, the PWM output being controlled goes to 100% and remains at 100% until the temperature drops below THERM - hysteresis. For acoustic reasons, it is recommended that the hysteresis value not be programmed to less than 4C. Setting the hysteresis value lower than 4C causes the fan to switch on and off regularly when the temperature is close to TMIN. 2 These registers become read-only registers when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 44. Register 0x6D--Remote 1 and Local Temperature Hysteresis Bit
<3:0> <7:4>
Name
HYSL HYSR1
R/W1
Read/write Read/write
Description
Local temperature hysteresis. 0C to 15C of hysteresis can be applied to the local temperature AFC and dynamic TMIN control loops. Remote 1 temperature hysteresis. 0C to 15C of hysteresis can be applied to the Remote 1 temperature AFC and dynamic TMIN control loops.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 45. Register 0x6E--Remote 2 Temperature Hysteresis Bit
<7:4>
Name
HYSR2
R/W1
Read/write
Description
Local temperature hysteresis. 0C to 15C of hysteresis can be applied to the local temperature AFC and dynamic TMIN control loops.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 46. Register 0x6F--XNOR Tree Test Enable (Power-On Default = 0x00)
Bit
<0> <7:1>
1
Name
XEN Reserved
R/W1
Read/write Read only
Description
If the XEN bit is set to 1, the device enters the XNOR tree test mode. Clearing the bit removes the device from the XNOR tree test mode. Unused. Do not write to these bits.
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 3 | Page 71 of 77 | www.onsemi.com
ADT7467
Table 47. Register 0x70--Remote 1 Temperature Offset (Power-On Default = 0x00)
Bit
<7:0>
R/W1
Read/write
Description
Allows a twos complement offset value to be automatically added to or subtracted from the Remote 1 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5C.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 48. Register 0x71--Local Temperature Offset (Power-On Default = 0x00)
Bit
<7:0>
R/W1
Read/write
Description
Allows a twos complement offset value to be automatically added to or subtracted from the local temperature reading. LSB value = 0.5C.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 49. Register 0x72--Remote 2 Temperature Offset (Power-On Default = 0x00)
Bit
<7:0>
R/W1
Read/write
Description
Allows a twos complement offset value to be automatically added to or subtracted from the Remote 2 temperature reading. This is to compensate for any inherent system offsets such as PCB trace resistance. LSB value = 0.5C.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 50. Register 0x73--Configuration Register 2 (Power-On Default = 0x00)
Bit
<0>
Name
AIN1
R/W1
Read/write
Description
AIN1 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN1 = 1, Pin 6 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (0x7D). Only relevant in low frequency mode. AIN2 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN2 = 1, Pin 7 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (0x7D). Only relevant in low frequency mode. AIN3 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN3 = 1, Pin 4 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (0x7D). Only relevant in low frequency mode. AIN4 = 0, speed of 3-wire fans measured using the TACH output from the fan. AIN4 = 1, Pin 9 is reconfigured to measure the speed of 2-wire fans using an external sensing resistor and coupling capacitor. AIN voltage threshold is set via Configuration Register 4 (0x7D). Only relevant in low frequency mode. AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows measurements on each channel to be made much faster. ATTN = 1, the ADT7467 removes the attenuators from the VCCP input. The VCCP input can be used for other functions such as connecting external sensors. CONV = 1, the ADT7467 is put into a single-channel ADC conversion mode. In this mode, the ADT7467 can be set to read continuously from one input only, for example, Remote 1 temperature. The appropriate ADC channel is selected by writing to bits <7:5> of the TACH1 minimum high byte register (0x55). Bits <7:5>, Register 0x55 000 Reserved 001 VCCP 010 VCC (3.3 V) 011 Reserved 100 Reserved 101 Remote 1 temperature 110 Local temperature 111 Remote 2 temperature
<1>
AIN2
Read/write
<2>
AIN3
Read/write
<3>
AIN4
Read/write
<4> <5> <6>
AVG ATTN CONV
Read/write Read/write Read/write
<7>
SHDN
Read/write
SHDN = 1, ADT7467 goes into shutdown mode. All PWM outputs assert low (or high depending on the state of the INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to indicate that the fans are not being driven.
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 3 | Page 72 of 77 | www.onsemi.com
ADT7467
Table 51. Register 0x74--Interrupt Mask 1 Register (Power-On Default = 0x00)
Bit
<1> <2> <4> <5> <6> <7>
Name
VCCP VCC R1T LT R2T OOL
R/W
Read/write Read/write Read/write Read/write Read/write Read/write
Description
VCCP = 1 masks SMBALERT for out-of-limit conditions on the VCCP channel. VCC = 1 masks SMBALERT for out-of-limit conditions on the VCC channel. R1T = 1 masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel. LT = 1 masks SMBALERT for out-of-limit conditions on the local temperature channel. R2T = 1 masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel. OOL = 1 masks SMBALERT for any out-of-limit condition in Interrupt Status Register 2.
Table 52. Register 0x75--Interrupt Mask 2 Register (Power-On Default = 0x00)
Bit
<1> <2> <3> <4> <5> <6> <7>
Name
OVT FAN1 FAN2 FAN3 F4P D1 D2
R/W
Read/write Read/write Read/write Read/write Read/write Read/write Read/write
Description
OVT = 1 masks SMBALERT for overtemperature THERM conditions. FAN1 = 1 masks SMBALERT for a Fan 1 fault. FAN2 = 1 masks SMBALERT for a Fan 2 fault. FAN3 = 1 masks SMBALERT for a Fan 3 fault. F4P = 1 masks SMBALERT for a Fan 4 fault. If the TACH4 pin is used as the THERM input, this bit masks SMBALERT for a THERM timer event. D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel. D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 53. Register 0x76--Extended Resolution Register 1 (Power-On Default = 0x00)1
Bit
<3:2> <5:4>
1
Name
VCCP VCC
R/W
R/W R/W
Description
VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement. VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 54. Register 0x77--Extended Resolution Register 2 (Power-On Default = 0x00)1
Bit
<3:2> <5:4> <7:6>
1
Name
TDM1 LTMP TDM2
R/W
R/W R/W R/W
Description
Remote 1 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement. Local temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement. Remote 2 temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.
If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
Table 55. Register 0x78--Configuration Register 3 (Power-On Default = 0x00)
Bit
<0> <1>
Name
ALERT Enable THERM
R/W1
Read/write Read/write
Description
ALERT = 1, Pin 5 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate out-of-limit error conditions. THERM Enable = 1 enables THERM timer monitoring functionality on Pin 9. Also determined by Bit 0 and Bit 1 (Pin 9 Func) of Configuration Register 4. When THERM is asserted, the fans run at full speed if the fans are running and the boost bit is set. Alternatively, THERM can be programmed so that a timer is triggered to time how long THERM has been asserted. When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum programmed duty cycle for fail-safe cooling. FAST = 1 enables fast TACH measurements on all channels. This increases the TACH measurement rate from once per second to once every 250 ms (4 x). DC1 = 1 enables TACH measurements to be continuously made on TACH1. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC2 = 1 enables TACH measurements to be continuously made on TACH2. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC3 = 1 enables TACH measurements to be continuously made on TACH3. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors. DC4 = 1 enables TACH measurements to be continuously made on TACH4. Fans must be driven by dc. Setting this bit prevents pulse stretching, because it is not required for dc-driven motors.
<2> <3> <4> <5> <6> <7>
BOOST FAST DC1 DC2 DC3 DC4
Read/write Read/write Read/write Read/write Read/write Read/write
1
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 3 | Page 73 of 77 | www.onsemi.com
ADT7467
Table 56. Register 0x79--THERM Timer Status Register (Power-On Default = 0x00)
Bit
<7:1> <0>
Name
TMR ASRT/TMR0
R/W
Read only Read only
Description
Times how long THERM input is asserted. These seven bits read 0 until the THERM assertion time exceeds 45.52 ms. This bit is set high upon the assertion of the THERM input and is cleared upon a read. If the THERM assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of 22.76 ms.
Table 57. Register 0x7A--THERM Timer Limit Register (Power-On Default = 0x00)
Bit
<7:0>
Name
LIMT
R/W
Read/write
Description
Sets the maximum THERM assertion length before an interrupt is generated. This is an 8-bit limit with a resolution of 22.76 ms, allowing THERM assertion limits of 45.52 ms to 5.82 sec to be programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2 (0x42) is set. If the limit value is 0x00, an interrupt is generated immediately upon the assertion of the THERM input.
Table 58. Register 0x7B--TACH Pulses per Revolution Register (Power-On Default = 0x55)
Bit
<1:0>
Name
FAN1
R/W
Read/write
Description
Sets the number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan pulses per revolution for an unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4
<3:2>
FAN2
Read/write
Sets the number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan pulses per revolution for an unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4
<5:4>
FAN3
Read/write
Sets the number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan pulses per revolution for an unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4
<7:6>
FAN4
Read/write
Sets the number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan pulses per revolution for an unknown fan type. Pulses Counted 00 = 1 01 = 2 (default) 10 = 3 11 = 4
Table 59. Register 0x7C--Configuration Register 5 (Power-On Default = 0x00)
Bit
<0>
Name
Twos Compl
R/W1
Read/write
Description
Twos Compl = 1 sets the temperature range to twos complement temperature range. Twos Compl = 0 changes the temperature range to Offset 64. When this bit is changed, the ADT7467 interprets all relevant temperature register values as defined by this bit. Sets the PWM drive frequency to high frequency mode (0) or low frequency mode (1). GPIO direction. When GPIO function is enabled, this determines whether the GPIO is an input (0) or an output (1). GPIO polarity. When the GPIO function is enabled and programmed as an output, this bit determines whether the GPIO is active low (0) or high (1). Unused.
<1> <2> <3> <4:7>
1
LF/HF GPIOD GPIOP RES
Read/write Read/write Read/write Read/write
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Rev. 3 | Page 74 of 77 | www.onsemi.com
ADT7467
Table 60. Register 0x7D--Configuration Register 4 (Power-On Default = 0x00) Bit <1:0> Name Pin 9 Func R/W1 Read/write Description These bits set the functionality of Pin 9. 00 = TACH4 (default). 01 = bidirectional THERM. 10 = SMBALERT. <3:2> AINL Read/write 11 = GPIO. These two bits define the input threshold for 2-wire fan speed measurements (low frequency mode only). 00 = 20 mV. 01 = 40 mV. 10 = 80 mV. 11 = 130 mV. Unused. Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to 2.2965 V (0xFF). Unused.
<4> <5> <6:7>
1
RES BpAtt VCCP RES
This register becomes a read-only register when the Configuration Register 1 LOCK bit is set to 1. Any subsequent attempts to write to this register fail.
Table 61. Register 0x7E--Manufacturer's Test Register 1 (Power-On Default = 0x00)
Bit <7:0> Name Reserved R/W Read only Description Manufacturer's test register. These bits are reserved for the manufacturer's testing purposes and should not be written to under normal operation.
Table 62. Register 0x7F--Manufacturer's Test Register 2 (Power-On Default = 0x00) Bit <7:0> Name Reserved R/W Read only Description Manufacturer's test register. These bits are reserved for the manufacturer's testing purposes and should not be written to under normal operation.
Rev. 3 | Page 75 of 77 | www.onsemi.com
ADT7467
CONFIGURATION 2 (0x73) VCC LOW LIMIT (0x48) VCC HIGH LIMIT (0x49) TEMPERATURE MEASUREMENT HIGH LIMIT LOW LIMIT (0x4E TO 0X53) RESCALE VCCP INPUT (5V/3.3V) SINGLE-CHANNEL ADC MODE SHUTDOWN AVERAGE TEMP AND VOLTAGE MEASUREMENTS MEASURE FROM 2- OR 3WIRE FANS
VCCP FANTACH 16-BIT MINIMUM LIMIT (0x54 TO 0X5B) INVERT PWM OUTPUT PWM CONFIGURATION (0x5C TO 0x5E) SLOW IMPROVED ACOUSTIC RAMP-UP FAN BEHAVIOR NO TIMEOUT 100ms 250ms (DEFAULT) SOFTWARE INTERRUPTS THERM TIMER LIMIT HAS BEEN EXCEEDED TEMPERATURE MEASURED IS OUT OF LIMITS DIODE FAULT. FOR REMOTE CHANNELS ONLY FAN FAULT INTERRUPT STATUS (0x41, 0x42) MASK INTERRUPT? (0x74,0x75) F4P INTERRUPTS ON STATUS REGISTER 2 400ms 1 PULSE PER REV 667ms 1s 2s 4s FASTEST SPEED CALCULATED BY ALL 3 TEMPERATURE CHANNEL CONTROLS MANUAL MODE. PWM DUTY CYCLE REGISTERS (0x30 TO 0x32) BECOME WRITABLE RUN FANS AT FULLSPEED RESCALE VCC (5V/3.3V) CONFIGURATION 3 (0x78) ENABLE THERM DYNAMIC T MIN CONTROL (0x36, 0x37) PHTXX CURRENT TEMPERATURE OF SELECTED CHANNEL IS COPIED TO RELEVANT OPERATING POINT REGISTER ON ASSERTION OF THERM FAST TACH MEASUREMENTS CONFIGURE PIN 10 ENABLE CONTINUOUS FAN SPEED MEASUREMENT PWM 2 SMBALERT ENABLE DYNAMIC T MIN CONTROL ON INDIVIDUAL CHANNEL THERM TIMER LIMIT (0x7A) THERM TIMER STATUS (0x79) VCCP LOW (SLEEP) INCREASE CYCLE TIME 16 CYCLES (2s) 32 CYCLES (4s) 64 CYCLES (8s) 128 CYCLES (16s) 256 CYCLES (32s) 512 CYCLES (64s) 1024 CYCLES (128s) 2048 CYCLES (256s) TEMPERATURE VOLTAGES FANS INTERRUPT GENERAL THERM MIN PWM 0% DUTY CYCLE THYST TMIN THYST TTHERM DECREASE CYCLE TIME CYXX TMIN ADJUSTMENT CYCLE TIME CHANGE CYCLE TIME 8 CYCLES (1s) 16 CYCLES (2s) 32 CYCLES (4s) 64 CYCLES (8s) 128 CYCLES (16s) 256 CYCLES (32s) 512 CYCLES (64s) 1024 CYCLES (128s) 100% DUTY CYCLE MAX PWM AUTOMATIC FAN CONTROL TEMPERATURE HEATING THERM BOOST (FAN MUST BE RUNNING) CONFIGURATION 4 (0x7D) SET PIN 14/PIN 20 FUNCTIONALITY HARDWARE INTERRUPTS THERM TACH4 THERM SMBALERT GPIO CONFIGURATION 5 (0x7C) TEMPERATURE RANGE 20mV 40mV 80mV 130mV BYPASS VCCP ATTENUATOR INPUT THRESHOLD FOR 2-WIRE FANS (AINL) FAN DRIVE HIGH/LOW FREQUENCY MODE GPIO DIRECTION GPIO POLARITY OFFSET 64 TWOS COMPLEMENT SMBALERT READY LOCK SETTINGS FASTEST SPEED CALCULATED BY LOCAL AND REMOTE 2 TEMP CONTROLS SELECTED PWM DRIVE START MONITORING SELECTED PWM DRIVE DISABLED (DEFAULT) CONFIGURATION 1 (0x40) 2 PULSES PER REV 3 PULSES PER REV 4 PULSES PER REV MAX FAN SPEED (MAX PWM DUTY CYCLE) (0x38 TO 0x3A) PWM DUTY CYCLE (MANUAL MODE ONLY) (0x30 TO 0x32) FAN TACH PULSES PER REV (0x7B) SELECTED PWM DRIVE RUNS FULL SPEED REMOTE 2 TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) LOCAL TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) MEASUREMENT LSBs (0x77) TEMPERATURE MEASUREMENT (0x25, 0x26,0x27) FAN SPINUP TIMEOUT
IF THESE REGISTERS ARE USED, ALL TEMPERATURE MEASUREMENT MSB REGISTERS ARE FROZEN UNTIL ALL TEMPERATURE MEASUREMENT MSB REGISTERS ARE READ.
VCC VCC MEASUREMENT (0x22)
TEMPERATURE OFFSET (0x70 TO 0x72)
REMOTE TEMP1
FAN 16-BIT MEASUREMENT (0x28 TO 0x2F)
REMOTE TEMP2 REMOTE 1 TEMP CONTROLS SELECTED PWM DRIVE (AFC MODE) MEASUREMENT MSBs (0x25 TO 0x27)
LOCAL TEMP
LOW BYTE MUST BE READ FIRST. WHEN THE LOW BYTE IS READ, REGISTERS ARE LOCKED UNTIL THE ASSOCIATED HIGH BYTE IS READ.
SELECTED PWM RAMP-UP SPEED
35s (33%-100%)
17.6s (33%-100%)
ENHANCED ACOUSTICS (0x62,0x63)
11.8s (33%-100%)
ENABLE SELECTED PWM RAMP-UP SPEED
7s (33%-100%)
SYNC FAN SPEED MEASUREMENTS
4.4s (33%-100%)
DRIVE PWM OUTPUTS HIGH/LOW
3s (33%-100%)
1.6s (33%-100%)
ALLOW SELECTED PWM TO TURN OFF WHEN TEMP IS BELOW TMIN-HYST
0.8s (33%-100%)
ADT7467 PROGRAMMING BLOCK DIAGRAM
TMIN. MIN TEMP THAT CAUSES SELECTED FANS TO RUN (0x67 TO 0x69) PWMMIN DUTY CYCLE (AUTOMATIC MODE ONLY) (0x64 TO 0x66)
TEMPERATURE HYSTERESIS (THYST) (0x6D, 0x6E)
AUTOMATIC FAN CONTROL
Figure 84.Block Diagram
(ONLY USED WHEN FANS ARE POWERED BY DC AND NOT PWM)
OPERATING POINT (0x33 TO 0x35)
TEMP TRANGE ,PWM FREQ,THERMENABLE (0x5F, 0x60, 0x61)
THERM IS INPUT/OUTPUT
04498-044
ADT7467/ADT7468 PROGRAMMING BLOCK DIAGRAM
PWM DUTY CYCLE/RELATIVE FAN SPEED COOLING TRANGE = SLOPE
Rev. 3 | Page 76 of 77 | www.onsemi.com
VCCP MEASUREMENT (0x47) VCCP HIGH LIMIT (0x47) VCCP LOW LIMIT (0x46) THERM TEMP LIMITS (0x6A, 0x6B, 0x6C) XNOR TEST (0x6F) AVERAGE TEMP AND VOLTAGE MEASUREMENTS (SEE CONFIGURATION 2, 0x73)
2C
TRANGE
2.5C
THERM AS (TIMER) INPUT
PWM FREQUENCY
11.0Hz
3.33C
14.7Hz
4C
22.1Hz
5C
29.4Hz
6.67C
35.3Hz
8C
44.1Hz
10C
58.8Hz
13.33C
THERM AS OVERTEMP OUTPUT
88.2Hz
16C
20C
26.67C
32C
40C
53.33C
80C
ADT7467 OUTLINE DIMENSIONS
0.197 0.193 0.189
16
9
1
0.158 0.154 0.150
8
0.244 0.236 0.228
PIN 1 0.065 0.049 0.069 0.053 8 0
0.010 0.025 0.004 BSC COPLANARITY 0.004
0.012 0.008
SEATING PLANE
0.010 0.006
0.050 0.016
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 85. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches
ORDERING GUIDE
Model ADT7467ARQ ADT7467ARQ-REEL ADT7467ARQ-REEL7 ADT7467ARQZ1 ADT7467ARQZ-REEL1 ADT7467ARQZ-R71 EVAL-ADT7467EBZ1
1
Temperature Range -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C -40C to +120C
Package Description 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP 16-Lead QSOP Evaluation Board
Package Option RQ-16 RQ-16 RQ-16 RQ-16 RQ-16 RQ-16
Z = RoHS Compliant Part.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
Rev. 3 | Page 77 of 77 | www.onsemi.com

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